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参数资料
| 型号： | ICS8430AY-51LF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 600 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| 封装： | 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32 |
| 文件页数： | 2/16页 |
| 文件大小： | 179K |
| 代理商： | ICS8430AY-51LF |
8430AY-51
www.icst.com/products/hiperclocks.html
REV. D FEBRUARY 11, 2003
10
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8430-51
600MHZ, LOW JITTER
LVCMOS/LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
FIGURE 5B. LVPECL OUTPUT TERMINATION
3.3V
F
OUT
F
IN
5
2 Zo
Z
o
5
2
Z
o
3
2
Z
o
3
2
Z
o = 50
Z
o = 50
Z
o = 50
Z
o = 50
FIGURE 5A. LVPECL OUTPUT TERMINATION
RTT =
1
(V
OH + VOL / VCC –2) –2
Z
o
Z
o = 50
Z
o = 50
50
50
RTT
V
CC - 2V
F
IN
F
OUT
Z
o = 50
Z
o = 50
drive 50
transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion.
Figures 5A and 5B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
TERMINATION FOR LVPECL OUTPUTS
The schematic of the ICS8430-51 layout example used in
this layout guideline is shown in
Figure 6A. The ICS8430-51
recommended PCB board layout for this example is shown
in
Figure 6B. This layout example is used as a general guide-
LAYOUT GUIDELINE
FIGURE 6A. SCHEMATIC OF RECOMMENDED LAYOUT
TL2
Zo = 50 Ohm
X1
R1
125
Termination
B (Not shown
in the layout)
S_LOAD
U1
8430-01
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
32
31
30
29
28
27
26
25
M5
M6
M7
M8
N0
N1
N2
GND
TEST
VCC
FO
UT1
nF
O
U
T
1
VCCO
FO
UT0
nF
O
U
T
0
GND
MR
S_CLOCK
S_DATA
S_LOAD
VCCA
nXTAL_SEL
REF_IN
XTAL1
M4
M3
M2
M1
M0
VCO_
SEL
nP
_LO
A
D
XTAL
2
IN-
R1
50
VDD
FO
UTN
C15
0.1u
TEST
S_CLOCK
C11
0.01u
S_DATA
R7
10
C14
0.1u
FO
UT
VDD
R3
125
VDD
R4
84
IN+
Termination A
IN-
TL1
Zo = 50 Ohm
R2
50
MR
REF_IN
C16
22u
R3
50
VDD
R2
84
IN+
XTAL_SEL
line. The layout in the actual system will depend on the
selected component types, the density of the components,
the density of the traces, and the stack up of the P.C. board.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS8430AY-51T | 制造商:ICS 制造商全称:ICS 功能描述:600MHZ, LOW JITTER LVCMOS/ LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| ICS8430AY-61 | 制造商:Integrated Device Technology Inc 功能描述: |
| ICS8430AY-61LF | 功能描述:IC SYNTHESIZR DUAL LVPECL 32LQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:HiPerClockS™ 标准包装:2,000 系列:- 类型:PLL 频率合成器 PLL:是 输入:晶体 输出:时钟 电路数:1 比率 - 输入:输出:1:1 差分 - 输入:输出:无/无 频率 - 最大:1GHz 除法器/乘法器:是/无 电源电压:4.5 V ~ 5.5 V 工作温度:-20°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-LSSOP（0.175"，4.40mm 宽） 供应商设备封装:16-SSOP 包装:带卷 (TR) 其它名称:NJW1504V-TE1-NDNJW1504V-TE1TR |
| ICS8430AY-61LFT | 功能描述:IC SYNTHESIZER LVPECL 32-LQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:HiPerClockS™ 标准包装:1,000 系列:- 类型:时钟/频率合成器，扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP（8x8） 包装:带卷 (TR) 其它名称:844S012AKI-01LFT |
| ICS8430AY-62LF | 功能描述:IC SYNTHESIZER LVPECL 32-LQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:HiPerClockS™ 标准包装:1,000 系列:- 类型:时钟/频率合成器，扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP（8x8） 包装:带卷 (TR) 其它名称:844S012AKI-01LFT |
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