- 您现在的位置：买卖IC网 > PDF目录65532 > ICS8430BY-01T 500 MHz, OTHER CLOCK GENERATOR, PQFP32 PDF资料下载
参数资料
| 型号： | ICS8430BY-01T |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 500 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| 封装： | 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, MS-026, LQFP-32 |
| 文件页数： | 3/10页 |
| 文件大小： | 111K |
| 代理商： | ICS8430BY-01T |
ICS8430CY-01
www.icst.com/products/hiperclocks.html
REV. C JULY 6, 2001
2
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8430-01
500 MHZ, LOW JITTER
LVPECL FREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes operation using a 16MHz crystal. Valid PLL loop divider values for
different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 6, NOTE 1 and NOTE 2.
The ICS8430-01 features a fully integrated PLL and therefore requires no external component for setting the loop bandwidth.
A parallel-resonant , fundamental crystal is used as the input to the on-chip oscillator. The output of the oscillator is divided by
16 prior to the phase detector. With a 16MHz crystal this provides a 1MHz reference frequency. The VCO of the PLL operates
over a range of 250MHz to 500MHz. The output of the loop divider is also applied to the phase detector.
The phase detector and the loop filter force the VCO output frequency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve lock. The output of
the VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides a 50% output
duty cycle.
The programmable features of the ICS8430-01 support two input modes and programmable PLL loop divider and output
divider. The two input operational modes are parallel and serial. Figure 1 shows the timing diagram for each mode. In parallel
mode the nP_LOAD input is initially LOW. The data on inputs M0 through M8 and N0 through N2 is passed directly to the ripple
counter. On the LOW-to-HIGH transition of the nP_LOAD input the data is latched and the ripple counter remains loaded until
the next LOW transition on nP_LOAD or until a serial event occurs. As a result the M and N bits can be hardwired to set the
ripple counter to a specific default state that will automatically occur during power-up. The TEST output is LOW when operat-
ing in the parallel input mode. The relationship between the VCO frequency, the crystal frequency and the loop divider is
defined as follows:
The M count and the required values of M0 through M8 are shown in Table4B, Programmable VCO Frequency Function.
Valid M values for which the PLL will achieve lock are defined as 250
≤ M ≤ 500. The frequency out is defined as follows:
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the
S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the ripple counter when
S_LOAD transitions from LOW-to-HIGH. The ripple counter divide values are latched on the HIGH-to-LOW transition of
S_LOAD. If S_LOAD is held HIGH data at the S_DATA input is passed directly to the ripple counter on each rising edge of
S_CLOCK. The serial mode can be used to program the M and N bits and test bits T1 and T0. The internal registers T0 and
T1 determine the state of the TEST output as follows:
16
M
fVCO =
fxtal x
N
fout =
fVCO
=
16
M
fxtal x
N
T1
T0
TEST Output
0
LOW
0
1
S_Data
1
0
Output of M divider
1
CMOS Fout
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
T1
T0
N 2
N 1
N 0
M8
M7
M6
M5
M4
M3
M2
M1
M0
S_DATA
S_CLOCK
S_LOAD
M0:M8, N0:N2
nP_LOAD
Time
相关PDF资料 |
PDF描述 |
|---|---|
| ICS8431AM-01LF | 200 MHz, OTHER CLOCK GENERATOR, PDSO28 |
| ICS8431AM-01LF | 200 MHz, OTHER CLOCK GENERATOR, PDSO28 |
| ICS8431AM-01 | 200 MHz, OTHER CLOCK GENERATOR, PDSO28 |
| ICS8432AY-101T | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| ICS8432BY-21 | 500 MHz, OTHER CLOCK GENERATOR, PQFP32 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS8430BY-71 | 制造商:ICS 制造商全称:ICS 功能描述:700MHZ, LOW JITTER, CRYSTAL INTERFACE / LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| ICS8430BY71L | 制造商:ICS 制造商全称:ICS 功能描述:700MHZ, LOW JITTER, CRYSTAL INTERFACE / LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| ICS8430BY-71LF | 功能描述:IC SYNTHESIZR DUAL LVPECL 32LQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:HiPerClockS™ 标准包装:1,000 系列:- 类型:时钟/频率合成器，扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP（8x8） 包装:带卷 (TR) 其它名称:844S012AKI-01LFT |
| ICS8430BY-71LFT | 功能描述:IC SYNTHESIZER DUAL 32-LQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:HiPerClockS™ 标准包装:1,000 系列:- 类型:时钟/频率合成器，扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP（8x8） 包装:带卷 (TR) 其它名称:844S012AKI-01LFT |
| ICS8430BY-71T | 制造商:ICS 制造商全称:ICS 功能描述:700MHZ, LOW JITTER, CRYSTAL INTERFACE / LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
发布紧急采购，3分钟左右您将得到回复。