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参数资料
| 型号： | ICS8430DY-01T |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 500 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| 封装： | 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32 |
| 文件页数： | 2/16页 |
| 文件大小： | 181K |
| 代理商： | ICS8430DY-01T |
8430DY-01
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 7, 2003
10
Integrated
Circuit
Systems, Inc.
ICS8430-01
500MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
The following component footprints are used in this layout
example: All the resistors and capacitors are size 0603.
POWER AND GROUNDING
Place the decoupling capacitors C14 and C15 as close as pos-
sible to the power pins. If space allows, placing the decoupling
capacitor at the component side is preferred. This can reduce
unwanted inductance between the decoupling capacitor and the
power pin generated by the via.
Maximize the pad size of the power (ground) at the decoupling
capacitor. Maximize the number of vias between power (ground)
and the pads. This can reduce the inductance between the power
(ground) plane and the component power (ground) pins.
If V
CCA shares the same power supply with VCC, insert the RC
filter R7, C11, and C16 in between. Place this RC filter as close
to the V
CCA pin as possible.
CLOCK TRACES AND TERMINATION
The component placements, locations and orientations should be
arranged to achieve the best clock signal quality. Poor clock signal
quality can degrade the system performance or cause system fail-
ure. In the synchronous high-speed digital system, the clock signal
is less tolerable to poor signal quality than other signals. Any ring-
ing on the rising or falling edge or excessive ring back can cause
system failure. The trace shape and the trace delay might be re-
stricted by the available space on the board and the component
location. While routing the traces, the clock signal traces should be
routed first and should be locked prior to routing other signal traces.
The traces with 50
transmission lines TL1 and TL2 at
FOUT and nFOUT should have equal delay and run ad-
jacent to each other. Avoid sharp angles on the clock trace.
Sharp angle turns cause the characteristic impedance to
change on the transmission lines.
Keep the clock trace on the same layer. Whenever pos-
sible, avoid any vias on the clock traces. Any via on the
trace can affect the trace characteristic impedance and
hence degrade signal quality.
To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow more space between the clock trace
and the other signal trace.
Make sure no other signal trace is routed between the
clock trace pair.
The matching termination resistors R1, R2, R3 and R4 should
be located as close to the receiver input pins as possible. Other
termination schemes can also be used but are not shown in
this example.
CRYSTAL
The crystal X1 should be located as close as possible to the pins
24 (XTAL1) and 25 (XTAL2). The trace length between the X1
and U1 should be kept to a minimum to avoid unwanted parasitic
inductance and capacitance. Other signal traces should not be
routed near the crystal traces.
FIGURE 5B. PCB BOARD LAYOUT FOR ICS8430-01
TL1, TL2 are 50 Ohm traces and
equal length
C15
C16
VCC
TL
1
R4
VIA
R7
R1
GND
U1
TL1
R3
X1
Close to the input
pins of the
receiver
C14
PIN 1
T
L1N
VCCA
TL1N
R2
C11
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| ICS8430DY-111LF | 8430 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
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| ICS8430DY-111LFT | 8430 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS8430DY-111 | 制造商:ICS 制造商全称:ICS 功能描述:700MHZ, LOW JITTER DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| ICS8430DY-111LF | 功能描述:IC SYNTHESIZER DUAL 32-LQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:HiPerClockS™ 标准包装:1,000 系列:- 类型:时钟/频率合成器，扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP（8x8） 包装:带卷 (TR) 其它名称:844S012AKI-01LFT |
| ICS8430DY-111LFT | 功能描述:IC SYNTHESIZER DUAL 32-LQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:HiPerClockS™ 标准包装:1,000 系列:- 类型:时钟/频率合成器，扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP（8x8） 包装:带卷 (TR) 其它名称:844S012AKI-01LFT |
| ICS8430DY-111T | 制造商:ICS 制造商全称:ICS 功能描述:700MHZ, LOW JITTER DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| ICS8430I-61 | 制造商:ICS 制造商全称:ICS 功能描述:500MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER |
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