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| 型号： | ICS8430DY-111LFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 8430 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封装： | 7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BBA, LQFP-32 |
| 文件页数： | 18/18页 |
| 文件大小： | 350K |
| 代理商： | ICS8430DY-111LFT |
IDT / ICS 3.3V LVPECL FREQUENCY SYNTHESIZER
9
ICS8430DY-111 REV. F JANUARY 29, 2007
ICS8430-111
700MHZ, LOW JITTER, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
APPLICATION INFORMATION
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8430-111 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
CC, VCCA, and VCCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance, power
supply isolation is required. Figure 2 illustrates how a 10
Ω
resistor along with a 10
μF and a .01μF bypass capacitor
should be connected to each V
CCA pin. The 10Ω resistor can
also be replaced by a ferrite bead.
POWER SUPPLY FILTERING TECHNIQUES
FIGURE 2. POWER SUPPLY FILTERING
10
Ω
V
CCA
10
μF
.01
μF
3.3V
.01
μF
V
CC
INPUTS:
TEST_CLK INPUT:
For applications not requiring the use of the test clock, it can be
left floating. Though not required, but for additional protection, a
1k
Ω resistor can be tied from the TEST_CLK to ground.
CLK/nCLK INPUT:
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required, but
for additional protection, a 1k
Ω resistor can be tied from CLK to
ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
Ω resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
LVPECL OUTPUT
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
相关PDF资料 |
PDF描述 |
|---|---|
| ICS8430DY-111T | 8430 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| ICS8430DY-11LF | 700 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| ICS8430DYI-01T | 500 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| ICS8430DYI-11 | 700 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| ICS8430DYI-11LFT | 700 MHz, OTHER CLOCK GENERATOR, PQFP32 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS8430DY-111T | 制造商:ICS 制造商全称:ICS 功能描述:700MHZ, LOW JITTER DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| ICS8430I-61 | 制造商:ICS 制造商全称:ICS 功能描述:500MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER |
| ICS8430I-71B | 制造商:ICS 制造商全称:ICS 功能描述:700MHZ, LOW JITTER, CRYSTAL INTERFACE / LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| ICS8430S07AKILF | 功能描述:IC CLK GENERATOR PLL 32VFQFN RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
| ICS8430S07AKILFT | 功能描述:IC CLK GENERATOR PLL 32VFQFN RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
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