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参数资料
| 型号： | ICS8430DYI-01T |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 500 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| 封装： | 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32 |
| 文件页数： | 16/16页 |
| 文件大小： | 179K |
| 代理商： | ICS8430DYI-01T |
8430DYI-01
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 10, 2003
9
Integrated
Circuit
Systems, Inc.
ICS8430I-01
500MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
The schematic of the ICS8430I-01 layout example used in
this layout guideline is shown in
Figure 5A. The ICS8430I-01
recommended PCB board layout for this example is shown in
Figure 5B. This layout example is used as a general guideline.
LAYOUT GUIDELINE
FIGURE 5A. SCHEMATIC OF RECOMMENDED LAYOUT
XTAL_SEL
S_DATA
C11
0.1u
R3
50
IN+
C14
0.1u
Termination A
R7
10
R2
84
IN+
R2
50
TEST
MR
R3
125
TL1
Zo = 50 Ohm
Termination B
(Not shown in
the layout)
S_CLOCK
FO
U
T
N
C15
0.1u
FO
U
T
R1
50
VC
C
REF_IN
IN-
VCC
IN-
VC
C
R4
84
X1
TL2
Zo = 50 Ohm
R1
125
U1
8430-01
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
32
31
30
29
28
27
26
25
M5
M6
M7
M8
N0
N1
N2
VEE
TEST
VC
C
FO
U
T
1
nFO
U
T1
V
CCO
FO
U
T
0
nFO
U
T0
VEE
MR
S_CLOCK
S_DATA
S_LOAD
VCCA
nXTAL_SEL
TEST_CLK
XTAL1
M4
M3
M2
M1
M0
VC
O
_
SEL
nP_LO
AD
XTAL2
C16
10u
S_LOAD
VCC0
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
FIGURE 4B. LVPECL OUTPUT TERMINATION
3.3V
F
OUT
F
IN
5
2 Zo
Z
o
5
2
Z
o
3
2
Z
o
3
2
Z
o = 50
Z
o = 50
FIGURE 4A. LVPECL OUTPUT TERMINATION
RTT =
1
(V
OH + VOL / VCC –2) –2
Z
o
50
50
RTT
V
CC - 2V
F
IN
F
OUT
drive 50
transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion.
Figures 4A and 4B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
TERMINATION FOR LVPECL OUTPUTS
Z
o = 50
Z
o = 50
The layout in the actual system will depend on the selected
component types, the density of the components, the density
of the traces, and the stack up of the P.C. board.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS8430I-61 | 制造商:ICS 制造商全称:ICS 功能描述:500MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER |
| ICS8430I-71B | 制造商:ICS 制造商全称:ICS 功能描述:700MHZ, LOW JITTER, CRYSTAL INTERFACE / LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| ICS8430S07AKILF | 功能描述:IC CLK GENERATOR PLL 32VFQFN RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
| ICS8430S07AKILFT | 功能描述:IC CLK GENERATOR PLL 32VFQFN RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
| ICS8430S07I | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:Clock Generator for Cavium Processors |
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