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参数资料
| 型号： | ICS843101AGI-312LFT |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 312.5 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| 封装： | 4.4 X 5 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-16 |
| 文件页数： | 3/17页 |
| 文件大小： | 314K |
| 代理商： | ICS843101AGI-312LFT |
843101AGI-312
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 1, 2005
11
Integrated
Circuit
Systems, Inc.
ICS843101I-312
FEMTOCLOCKSCRYSTAL-TO-LVPECL
312.5MHZ FREQUENCY MARGINING SYNTHESIZER
PRELIMINARY
TERMINATION FOR 3.3V LVPECL OUTPUT
V
CC - 2V
50
Ω
50
Ω
RTT
Z
o = 50Ω
Z
o = 50Ω
FOUT
FIN
RTT =
Z
o
1
((V
OH + VOL) / (VCC – 2)) – 2
3.3V
125
Ω
125
Ω
84
Ω
84
Ω
Z
o = 50Ω
Z
o = 50Ω
FOUT
FIN
The clock layout topology shown below is a typical ter-
mination for LVPECL outputs. The two different layouts
mentioned are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs
that generate ECL/LVPECL compatible outputs. There-
fore, terminating resistors (DC current path to ground)
or current sources must be used for functionality. These
FIGURE 4B. LVPECL OUTPUT TERMINATION
FIGURE 4A. LVPECL OUTPUT TERMINATION
outputs are designed to drive 50
Ω transmission lines.
Matched impedance techniques should be used to maxi-
mize operating frequency and minimize signal distor-
tion. Figures 4A and 4B show two different layouts which
are recommended only as guidelines. Other suitable
clock layouts may exist and it would be recommended
that the board designers simulate to guarantee compat-
ibility across all printed circuit and clock component pro-
cess variations.
INPUTS:
CRYSTAL INPUT:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating.
Though not required, but for additional protection, a 1k
Ω
resistor can be tied from XTAL_IN to ground.
CLK INPUT:
For applications not requiring the use of the test clock, it can
be left floating. Though not required, but for additional
protection, a 1k
Ω resistor can be tied from the CLK input to
ground.
RECOMMENDATIONS FOR UNUSED INPUT PINS
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
Ω resistor can be used.
相关PDF资料 |
PDF描述 |
|---|---|
| ICS843101AGI-312LF | 312.5 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| ICS843101IAG-100LFT | 100 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| ICS843101IAG-100LF | 100 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| ICS84314AY-02LF | 700 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| ICS84314AYLFT | 350 MHz, OTHER CLOCK GENERATOR, PQFP32 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS843101AGI-312T | 制造商:ICS 制造商全称:ICS 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER |
| ICS843101I-100 | 制造商:ICS 制造商全称:ICS 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TO-LVPECL 100MHZ FREQUENCY MARGINING SYNTHESIZER |
| ICS843101I-312 | 制造商:ICS 制造商全称:ICS 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER |
| ICS843101IAG-100 | 制造商:ICS 制造商全称:ICS 功能描述:FEMTOCLOCKS? CRYSTAL-TO-LVPECL 100MHZ FREQUENCY MARGINING SYNTHESIZER |
| ICS843101IAG-100LF | 制造商:ICS 制造商全称:ICS 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TO-LVPECL 100MHZ FREQUENCY MARGINING SYNTHESIZER |
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