参数资料
型号: ICS843156AKLFT
厂商: IDT, Integrated Device Technology Inc
文件页数: 16/20页
文件大小: 0K
描述: IC CLK GENERATOR 32VFQFP
标准包装: 2,500
系列: HiPerClockS™
类型: 时钟/频率合成器
PLL: 带旁路
输入: 晶体
输出: LVPECL
电路数: 1
比率 - 输入:输出: 1:10
差分 - 输入:输出: 无/是
频率 - 最大: 156.25MHz
除法器/乘法器: 是/无
电源电压: 2.375 V ~ 3.465 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-VFQFPN 裸露焊盘(4x4)
包装: 带卷 (TR)
ICS843156AK REVISION B NOVEMBER 28, 2012
5
2012 Integrated Device Technology, Inc.
ICS843156 Data Sheet
CRYSTAL-TO-LVPECL CLOCK SYNTHESIZER
AC Electrical Characteristics
Table 6A. AC Characteristics, VCC = VCCO = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: This parameter is defined in accordance with JEDEC standard 65.
NOTE 2: Refer to phase noise plot.
Table 6B. AC Characteristics, VCC = VCCO = 2.5V ± 5%, VEE = 0V, TA = 0°C to 70°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: This parameter is defined in accordance with JEDEC standard 65.
Table 6C. AC Characteristics, VCC = 3.3V ± 5%, VCCO = 2.5V ± 5%, VEE = 0V, TA = 0°C to 70°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: This parameter is defined in accordance with JEDEC standard 65.
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
fOUT
Output Frequency
156.25
MHz
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 1
40
ps
tjit()
RMS Phase Jitter, (Random);
NOTE 2
156.25MHz, Integration Range:
1.875MHz - 20MHz
0.39
ps
tR / tF
Output Rise/Fall Time
20% to 80%
200
700
ps
odc
Output Duty Cycle
45
55
%
tLOCK
PLL Lock Time
100
ms
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
fOUT
Output Frequency
156.25
MHz
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 1
35
ps
tjit()
RMS Phase Jitter, (Random)
156.25MHz, Integration Range:
1.875MHz - 20MHz
0.49
ps
tR / tF
Output Rise/Fall Time
20% to 80%
200
700
ps
odc
Output Duty Cycle
45
55
%
tLOCK
PLL Lock Time
100
ms
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
fOUT
Output Frequency
156.25
MHz
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 1
40
ps
tjit()
RMS Phase Jitter, (Random)
156.25MHz, Integration Range:
1.875MHz - 20MHz
0.40
ps
tR / tF
Output Rise/Fall Time
20% to 80%
200
700
ps
odc
Output Duty Cycle
45
55
%
tLOCK
PLL Lock Time
100
ms
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