参数资料
型号: ICS8431AM-21LF
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟产生/分配
英文描述: 350 MHz, OTHER CLOCK GENERATOR, PDSO28
封装: 7.50 X 18.05 MM, 2.25 MM HEIGHT, ROHS COMPLIANT, MS-013, MO-119, SOIC-28
文件页数: 12/19页
文件大小: 342K
代理商: ICS8431AM-21LF
IDT / ICS 3.3V LVPECL FREQUENCY SYNTHESIZER
2
ICS8431AM-21 REV. A MAY 30, 2007
ICS8431-21
350MHZ, LOW JITTER, CRYSTAL OSCILLATOR-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
puts M0 through M8. While the nP_LOAD input is held LOW,
the data present at M0:M8 is transparent to the M divider. On
the LOW-to-HIGH transition of nP_LOAD, the M0:M8 data is
latched into the M divider and any further changes at the M0:M8
inputs will not be seen by the M divider until the next LOW
transition on nP_LOAD.
The relationship between the VCO frequency, the crystal fre-
quency and the M divider is defined as follows:
The M value and the required values of M0:M8 for programming
the VCO are shown in Table 3B, Programmable VCO Frequency
Function Table. The frequency out is defined as follows:
For the ICS8431-21, the output divider may be set to either
÷2
or
÷4 by the DIV_SEL pin. For an input of 16 MHz, valid
M values for which the PLL will achieve lock are defined as:
250
≤ M ≤ 511.
FUNCTIONAL DESCRIPTION
The ICS8431-21 features a fully integrated PLL and therefore
requires no external components for setting the loop bandwidth.
The output of the oscillator is divided by 16 prior to the phase
detector. With a 16MHz crystal this provides a 1MHz reference
frequency. The VCO of the PLL operates over a range of 250MHz
to 700MHz. The output of the M divider is also applied to the
phase detector.
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency by adjusting
the VCO control voltage. Note that for some values of M (either
too high or too low), the PLL will not achieve lock. The output of
the VCO is scaled by a divider prior to being sent to the LVPECL
output buffer. The divider provides a 50% output duty cycle.
The programmable features of the ICS8431-21 support four
output operational modes and a programmable M divider and
output divider. The four output operational modes are spread
spectrum clocking (SSC), non-spread spectrum clock and
two test modes and are controlled by the SSC_CTL[1:0] pins.
The PLL loop divider or M divider is programmed by using in-
16
M
fVCO =
fxtal x
N
FOUT =
fVCO
=
16 x N
fxtal x M
相关PDF资料
PDF描述
ICS8431AMI-21LF 350 MHz, OTHER CLOCK GENERATOR, PDSO28
ICS8431CM-01LF 200 MHz, OTHER CLOCK GENERATOR, PDSO28
ICS8431CM-11T 255 MHz, OTHER CLOCK GENERATOR, PDSO28
ICS8431CM-11LFT 255 MHz, OTHER CLOCK GENERATOR, PDSO28
ICS8431DMI-01 200 MHz, OTHER CLOCK GENERATOR, PDSO28
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