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参数资料
| 型号： | ICS8431CM-11T |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 255 MHz, OTHER CLOCK GENERATOR, PDSO28 |
| 封装： | 7.50 X 18.05, 2.25 MM HEIGHT, SOIC-28 |
| 文件页数： | 11/18页 |
| 文件大小： | 2136K |
| 代理商： | ICS8431CM-11T |
8431CM-11
www.icst.com/products/hiperclocks.html
REV. B AUGUST 7, 2002
2
Integrated
Circuit
Systems, Inc.
ICS8431-11
255MHZ, LOW JITTER, CRYSTAL OSCILLATOR-
TO
-3.3V LVPECL FREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION
The ICS8431-11 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth.
A 16MHz series-resonant, fundamental crystal is used as the input to the on-chip oscillator. The output of the oscillator is divided by
16 prior to the phase detector. With a 16MHz crystal this provides a 1MHz reference frequency. The VCO of the PLL operates over
a range of 190MHz to 510MHz. The output of the M divider is also applied to the phase detector.
The phase detector and the M divider force the VCO output frequency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the
VCO is scaled by a divider prior to being sent to the LVPECL output buffer. The divider provides a 50% output duty cycle.
The programmable features of the ICS8431-11 support four output operational modes and a programmable M divider and
output divider. The four output operational modes are spread spectrum clocking (SSC), non-spread spectrum clock and
two test modes and are controlled by the SSC_CTL[1:0] pins.
The PLL loop divider or M divider is programmed by using inputs M0 through M8. While the nP_LOAD input is held LOW, the
data present at M0:M8 is transparent to the M divider. On the LOW-to-HIGH transition of nP_LOAD, the M0:M8 data is latched
into the M divider and any further changes at the M0:M8 inputs will not be seen by the M divider until the next LOW transition
on nP_LOAD.
The relationship between the VCO frequency, the crystal frequency and the M divider is defined as follows:
The M value and the required values of M0:M8 for programming the VCO are shown in
Table 3B, Programmable VCO Frequency
Function Table. The frequency out is defined as follows:
For the ICS8431-11, the output divider equals 2. Valid M values for which the PLL will achieve lock are defined as 190
≤ M ≤ 510.
16
M
fVCO =
fxtal x
2
FOUT =
fVCO
=
32
fxtal x M
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| ICS8431EM11 | 制造商:ICS 功能描述: |
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| ICS84320-01K | 制造商:ICS 制造商全称:ICS 功能描述:780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER |
| ICS843201AG-375LF | 功能描述:IC SYNTHESIZER 375MHZ 16-TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:HiPerClockS™, FemtoClock™ 标准包装:27 系列:Precision Edge® 类型:频率合成器 PLL:是 输入:PECL，晶体 输出:PECL 电路数:1 比率 - 输入:输出:1:1 差分 - 输入:输出:无/是 频率 - 最大:800MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 5.25 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:28-SOIC（0.295"，7.50mm 宽） 供应商设备封装:28-SOIC 包装:管件 |
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