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参数资料
| 型号： | ICS843207CY-350 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 375 MHz, OTHER CLOCK GENERATOR, PQFP48 |
| 封装： | 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-48 |
| 文件页数： | 16/16页 |
| 文件大小： | 266K |
| 代理商： | ICS843207CY-350 |
IDT / ICS LVPECL FREQUENCY MARGINING SYNTHESIZER
9
ICS843207CY-350 REV. A DECEMBER 3, 2007
ICS843207-350
FEMTOCLOCKS CRYSTAL-TO-LVPECL 350MHZ FREQUENCY MARGINING SYNTHESIZER
PRELIMINARY
INPUTS:
CRYSTAL INPUTS
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1k
Ω resistor can be tied
from XTAL_IN to ground.
REF_CLK INPUT
For applications not requiring the use of the reference clock,
it can be left floating. Though not required, but for additional
protection, a 1k
Ω resistor can be tied from the REF_CLK to
ground.
LVCMOS CONTROL PINS
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
Ω resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
LVPECL OUTPUTS
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS
signal through an AC couple capacitor. A general interface
diagram is shown in Figure 3. The XTAL_OUT pin can
be left floating. The input edge rate can be as slow as
10ns. For LVCMOS inputs, it is recommended that the
amplitude be reduced from full swing to half swing in order
to prevent signal interference with the power rail and to
reduce noise. This configuration requires that the output
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
impedance of the dr iver (Ro) plus the series resistance
(Rs) equals the transmission line impedance. In addition,
matched termination at the crystal input will attenuate the
signal in half. This can be done in one of two ways. First, R1
and R2 in parallel should equal the transmission line impedance.
For most 50
Ω applications, R1 and R2 can be 100Ω. This can
also be accomplished by removing R1 and making R2 50
Ω.
R2
Zo = 50
VDD
Ro
Zo = Ro + Rs
R1
VDD
XTAL_IN
XTAL_OUT
.1uf
Rs
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS843207CY-350LF | 功能描述:IC SYNTHESIZER 350MHZ 48-LQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:HiPerClockS™, FemtoClock™ 标准包装:27 系列:Precision Edge® 类型:频率合成器 PLL:是 输入:PECL，晶体 输出:PECL 电路数:1 比率 - 输入:输出:1:1 差分 - 输入:输出:无/是 频率 - 最大:800MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 5.25 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:28-SOIC（0.295"，7.50mm 宽） 供应商设备封装:28-SOIC 包装:管件 |
| ICS843207CY-350LFT | 功能描述:IC SYNTHESIZER 350MHZ 48-LQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:HiPerClockS™, FemtoClock™ 标准包装:27 系列:Precision Edge® 类型:频率合成器 PLL:是 输入:PECL，晶体 输出:PECL 电路数:1 比率 - 输入:输出:1:1 差分 - 输入:输出:无/是 频率 - 最大:800MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 5.25 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:28-SOIC（0.295"，7.50mm 宽） 供应商设备封装:28-SOIC 包装:管件 |
| ICS84320A01N | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER |
| ICS84320AI01 | 制造商:ICS 制造商全称:ICS 功能描述:780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL |
| ICS84320AK01 | 制造商:ICS 制造商全称:ICS 功能描述:780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER |
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