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参数资料
| 型号： | ICS84329BV-01T |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 700 MHz, OTHER CLOCK GENERATOR, PQCC28 |
| 封装： | 11.60 X 11.40 MM, 4.10 MM HEIGHT, PLASTIC, MS-018, LCC-28 |
| 文件页数： | 12/19页 |
| 文件大小： | 268K |
| 代理商： | ICS84329BV-01T |
84329BM-01
www.icst.com/products/hiperclocks.html
REV. A JUNE 10, 2005
2
Integrated
Circuit
Systems, Inc.
ICS84329B-01
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
M8 and N0 through N1 is passed directly to the M divider and
N output divider. On the LOW-to-HIGH transition of the
nP_LOAD input, the data is latched and the M divider remains
loaded until the next LOW transition on nP_LOAD or until a
serial event occurs. The TEST output is Mode 000 (shift reg-
ister out) when operating in the parallel input mode. The rela-
tionship between the VCO frequency, the crystal frequency
and the M divider is defined as follows:
The M value and the required values of M0 through M8 are
shown in Table 3B, Programmable VCO Frequency Function
Table. Valid M values for which the PLL will achieve lock are
defined as 250
≤ M ≤ 511. The frequency out is defined as
follows:
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the
shift register are loaded into the M divider when S_LOAD tran-
sitions from LOW-to-HIGH. The M divide and N output divide
values are latched on the HIGH-to-LOW transition of S_LOAD.
If S_LOAD is held HIGH, data at the S_DATA input is passed
directly to the M divider on each rising edge of S_CLOCK.
The serial mode can be used to program the M and N bits
and test bits T2:T0. The internal registers T2:T0 determine
the state of the TEST output as follows:
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes op-
eration using a 16MHz crystal. Valid PLL loop divider values
for different crystal or input frequencies are defined in the In-
put Frequency Characteristics, Table 6, NOTE 1.
The ICS84329B-01 features a fully integrated PLL and there-
fore requires no external components for setting the loop band-
width. A parallel resonant, fundamental crystal is used as the
input to the on-chip oscillator. The output of the oscillator is
divided by 16 prior to the phase detector. With a 16MHz crys-
tal this provides a 1MHz reference frequency. The VCO of
the PLL operates over a range of 250MHz to 700MHz. The
output of the M divider is also applied to the phase detector.
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency ÷ 16 by ad-
justing the VCO control voltage. Note that for some values of M
(either too high or too low), the PLL will not achieve lock. The
output of the VCO is scaled by a divider prior to being sent to
each of the LVPECL output buffers. The divider provides a 50%
output duty cycle.
The programmable features of the ICS84329B-01 support two
input modes to program the M divider and N output divider.
The two input operational modes are parallel and serial.
Fig-
ure 1 shows the timing diagram for each mode. In parallel mode
the nP_LOAD input is LOW. The data on inputs M0 through
16
M
fVCO =
fxtal x
N
fout =
fVCO
=
16
M
fxtal
x
N
T2
T1
T0
TEST Output
0
Shift Register Out
0
1
High
0
1
0
PLL Reference Xtal ÷ 16
0
1
VCO ÷ M, (non 50% Duty M divider)
1
0
fOUT, LVCMOS Output Frequency < 200MHz
10
1
Low
1
0
S_CLOCK ÷ M
(non 50% Duty Cycle M divider)
1
fOUT ÷ 4
fOUT
fOUT
S_CLOCK ÷ N divider
fOUT
Time
SERIAL LOADING
PARALLEL LOADING
t
S
t
H
t
S
t
H
t
S
M, N
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
S_CLOCK
S_DATA
S_LOAD
nP_LOAD
M0:M8, N0:N1
nP_LOAD
S_LOAD
T2
T1
T0
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
相关PDF资料 |
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| ICS84329BM-01 | 700 MHz, OTHER CLOCK GENERATOR, PDSO28 |
| ICS84329BM-01T | 700 MHz, OTHER CLOCK GENERATOR, PDSO28 |
| ICS84329BV-01 | 700 MHz, OTHER CLOCK GENERATOR, PQCC28 |
| ICS84329BM-01LF | 700 MHz, OTHER CLOCK GENERATOR, PDSO28 |
| ICS84329BM-01T | 700 MHz, OTHER CLOCK GENERATOR, PDSO28 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS84329BVLF | 功能描述:IC SYNTHESIZER 700MHZ 28-PLCC RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:HiPerClockS™ 标准包装:1,000 系列:- 类型:时钟/频率合成器，扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP（8x8） 包装:带卷 (TR) 其它名称:844S012AKI-01LFT |
| ICS84329BVLFT | 功能描述:IC SYNTHESIZER 700MHZ 28-PLCC RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:HiPerClockS™ 标准包装:1,000 系列:- 类型:时钟/频率合成器，扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP（8x8） 包装:带卷 (TR) 其它名称:844S012AKI-01LFT |
| ICS84329BVT | 制造商:ICS 制造商全称:ICS 功能描述:700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER |
| ICS84329BY | 制造商:ICS 制造商全称:ICS 功能描述:700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER |
| ICS84329BYLF | 功能描述:IC SYNTHESIZER GP LVPECL 32-LQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:HiPerClockS™ 标准包装:2,000 系列:- 类型:PLL 频率合成器 PLL:是 输入:晶体 输出:时钟 电路数:1 比率 - 输入:输出:1:1 差分 - 输入:输出:无/无 频率 - 最大:1GHz 除法器/乘法器:是/无 电源电压:4.5 V ~ 5.5 V 工作温度:-20°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-LSSOP（0.175"，4.40mm 宽） 供应商设备封装:16-SSOP 包装:带卷 (TR) 其它名称:NJW1504V-TE1-NDNJW1504V-TE1TR |
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