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| 型号： | ICS8432DY-101LFT |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 1/20页 |
| 文件大小： | 0K |
| 描述： | IC SYNTHESIZER 700MHZ 32-LQFP |
| 标准包装： | 1,000 |
| 系列： | HiPerClockS™ |
| 类型： | 频率合成器 |
| PLL： | 带旁路 |
| 输入： | HCSL，LVDS，LVHSTL，LVPECL，SSTL |
| 输出： | LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 700MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP |
| 供应商设备封装： | 32-TQFP（7x7） |
| 包装： | 带卷 (TR) |
| 其它名称： | 8432DY-101LFT |
700MHZ, DIFFERENTIAL-TO-3.3V
LVPECL FREQUENCY SYNTHESIZER
ICS8432-101
IDT / ICS 700MHZ, 3.3V LVPECL FREQUENCY SYNTHESIZER
1
ICS8432DY-101 REV. C APRIL 10, 2007
GENERAL DESCRIPTION
The ICS8432-101 is a general purpose, dual out-
put Differential-to-3.3V LVPECL high frequency
synthesizer and a member of the HiPerClockS
family of High Performance Clock Solutions from
ICS. The ICS8432-101 has a selectable TEST_CLK
or CLK, nCLK inputs. The TEST_CLK input accepts LVCMOS
or LVTTL input levels and translates them to 3.3V LVPECL lev-
els. The CLK, nCLK pair can accept most standard differen-
tial input levels. The VCO operates at a frequency range of
250MHz to 700MHz. The VCO frequency is programmed in
steps equal to the value of the input differential or single ended
reference frequency. The VCO and output frequency can be
programmed using the serial or parallel interfaces to the con-
figuration logic. The low phase noise characteristics of the
ICS8432-101 makes it an ideal clock source for Gigabit Ethernet
and SONET applications.
BLOCK DIAGRAM
PIN ASSIGNMENT
FEATURES
Dual differential 3.3V LVPECL outputs
Selectable CLK, nCLK or LVCMOS/LVTTL TEST_CLK
TEST_CLK can accept the following input levels:
LVCMOS or LVTTL
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
CLK, nCLK or TEST_CLK maximum input frequency: 40MHz
Output frequency range: 25MHz to 700MHz
VCO range: 250MHz to 700MHz
Accepts any single-ended input signal on CLK input with
resistor bias on nCLK input
Parallel interface for programming counter and output
dividers
RMS period jitter: 5ps (maximum)
Cycle-to-cycle jitter: 25ps (maximum)
3.3V supply voltage
0°C to 70°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
CLK
TEST_CLK
CLK_SEL
VCCA
S_LOAD
S_DATA
S_CLOCK
MR
M5
M6
M7
M8
N0
N1
nc
VEE
V
EE
nFOUT0
FOUT0
V
CCO
nFOUT1
FOUT1
V
CC
TEST
nCLK
nP_LO
A
D
VCO_SEL
M0
M1
M2
M3
M4
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
ICS8432-101
VCO_SEL
CLK_SEL
TEST_CLK
CLK
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M0:M8
N0:N1
VCO
PLL
FOUT0
nFOUT0
FOUT1
nFOUT1
TEST
CONFIGURATION
INTERFACE
LOGIC
÷ M
0
1
0
1
PHASE DETECTOR
÷1
÷2
÷4
÷8
MR
nCLK
HiPerClockS
ICS
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| ICS844001AGLFT | IC CLK GEN FIBRE CHAN 8-TSSOP |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS8432DY-101T | 制造商:ICS 制造商全称:ICS 功能描述:700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| ICS8432DYI-101 | 制造商:ICS 制造商全称:ICS 功能描述:700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| ICS8432DYI-101LF | 功能描述:IC SYNTHESIZER 700MHZ 32-LQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:HiPerClockS™ 标准包装:1,000 系列:- 类型:时钟/频率合成器，扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP（8x8） 包装:带卷 (TR) 其它名称:844S012AKI-01LFT |
| ICS8432DYI-101LFT | 功能描述:IC SYNTHESIZER 700MHZ 32-LQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:HiPerClockS™ 标准包装:1,000 系列:- 类型:时钟/频率合成器，扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP（8x8） 包装:带卷 (TR) 其它名称:844S012AKI-01LFT |
| ICS8432DYI-101T | 制造商:ICS 制造商全称:ICS 功能描述:700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
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