参数资料
型号: ICS8432DYI-101LF
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟及定时
英文描述: 8432 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
封装: 7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BBA, LQFP-32
文件页数: 4/20页
文件大小: 412K
代理商: ICS8432DYI-101LF
IDT / ICS 700MHZ, 3.3V LVPECL FREQUENCY SYNTHESIZER
12
ICS8432DYI-101 REV. C APRIL 10, 2007
ICS8432I-101
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
LAYOUT GUIDELINE
The schematic of the ICS8432I-101 layout example used in
this layout guideline is shown in Figure 6A. The ICS8432I-101
recommended PCB board layout for this example is shown in
Figure 6B. This layout example is used as a general guideline.
FIGURE 6A. SCHEMATIC OF RECOMMENDED LAYOUT
The layout in the actual system will depend on the selected
component types, the density of the components, the density
of the traces, and the stack up of the P.C. board.
C16
10u
Termination A
U1
8432-101
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
32
31
30
29
28
27
26
25
M5
M6
M7
M8
N0
N1
nc
VEE
TEST
VDD
FOUT1/2
nFOUT1/2
VCCO
FOUT
nFOUT
VEE
MR
S_CLOCK
S_DATA
S_LOAD
VDDA
nCLK_SEL
REF_IN
CLK
M4
M3
M2
M1
M0
VCO_SEL
nP_LOAD
nCLK
R1
125
VCCA
TL2
Zo = 50 Ohm
TEST
IN-
VCC
S_CLOCK
VCC
R3
125
C11
0.01u
XTAL_SEL
R3
50
S_LOAD
R7
10
TL1
Zo = 50 Ohm
MR
IN+
R4
84
FOUT
R2
84
S_DATA
R1
50
C15
0.1u
nCLK
CLK
VCC
IN+
Termination B
(not shown in
the layout)
FOUTN
R2
50
C14
0.1u
VCC
相关PDF资料
PDF描述
ICS8432DYI-101T 8432 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
ICS84330AM-01 700 MHz, OTHER CLOCK GENERATOR, PDSO28
ICS84330AM-01LF 700 MHz, OTHER CLOCK GENERATOR, PDSO28
ICS84330AVLF 700 MHz, OTHER CLOCK GENERATOR, PQCC28
ICS84330AY-03 700 MHz, OTHER CLOCK GENERATOR, PQFP32
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