参数资料
型号: ICS84330AY-03
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟产生/分配
英文描述: 700 MHz, OTHER CLOCK GENERATOR, PQFP32
封装: 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBA, LQFP-32
文件页数: 15/21页
文件大小: 481K
代理商: ICS84330AY-03
84330AY-03
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 2, 2006
3
Integrated
Circuit
Systems, Inc.
ICS84330-03
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
START (ST) – defined as high-to-low transition on SDA while holding SCL HIGH.
DATA - Between START and STOP cycles, SDA is synchronous with SCL.
Data may change only when SCL is LOW and must be stable when SCL is HIGH.
ACKNOWLEDGE (AK) – SDA is driven LOW before the SCL rising edge and
held LOW until the SCL falling edge.
STOP (SP) – defined as low-to-high transition on SDA while holding SCL HIGH.
Data Byte values latched into control registers here.
↑↑↑↑↑
I2C INTERFACE - PROTOCOL
The ICS84330-03 is a slave-only device and uses the stan-
dard I2C protocol as shown in the below diagrams. The maxi-
A serial transfer to the ICS84330-03 always consists of an
address cycle followed by 4 data bytes: 1 dummy byte fol-
lowed by 3 data bytes. Any additional bytes beyond the 4 data
bytes will not be acknowledged and the ICS84330-03 will
leave the data bus HIGH. These extra bits will not be loaded
into the serial control register. Once the 4 Data bytes are loaded
I2C INTERFACE - A WRITE EXAMPLE
mum SCL frequency is greater than 10MHz which is more
than sufficient for standard I2C clock speeds.
and the master generates a stop condition, the values in the
serial control register are latched into the M divider, N divider,
and control bits and the device will smoothly slew to the new
frequency and any changes to the state of the control bits will
take effect.
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SCL
SDA
START
Valid Data
Acknowledge
STOP
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N0
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1
ICS84330-03
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
TSD
IDT / ICS 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
ICS84330-03
3
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