参数资料
型号: ICS84334AYT
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟产生/分配
英文描述: 700 MHz, OTHER CLOCK GENERATOR, PQFP48
封装: 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-48
文件页数: 5/21页
文件大小: 335K
代理商: ICS84334AYT
84334BY
www.icst.com/products/hiperclocks.html
REV. A JULY 22, 2004
13
Integrated
Circuit
Systems, Inc.
ICS84334
MULTI-RATE LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS84334 provides sepa-
rate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
CC, VCCA, and VCCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 2 illustrates how
a 24
resistor along with a 10F and a .01F bypass
capacitor should be connected to each V
CCA pin.
POWER SUPPLY FILTERING TECHNIQUES
FIGURE 2. POWER SUPPLY FILTERING
24
V
CCA
10
F
.01
F
3.3V
.01
F
V
CC
APPLICATION INFORMATION
Figure 3 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
CC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVCMOS/LVTTL LEVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
CC = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
V_REF
R1
1K
C1
0.1u
R2
1K
Single Ended Clock Input
CLK
nCLK
VCC
FIGURE 3. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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