参数资料
型号: ICS843AG-106LF
元件分类: 时钟产生/分配
英文描述: 106.25 MHz, OTHER CLOCK GENERATOR, PDSO8
封装: 4.40 X 3 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-8
文件页数: 11/13页
文件大小: 191K
代理商: ICS843AG-106LF
843AG-106
www.icst.com/products/hiperclocks.html
REV. B APRIL 26, 2006
7
Integrated
Circuit
Systems, Inc.
ICS843-106
106.25MHZ, LVCMOS, LVPECL
DUAL OUTPUT OSCILLATOR
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
FIGURE 2B. LVPECL OUTPUT TERMINATION
FIGURE 2A. LVPECL OUTPUT TERMINATION
drive 50
Ω transmission lines.Matched impedance techniques
should be used to maximize operating frequency and mini-
mize signal distortion. Figures 2A and 2B show two different
layouts which are recommended only as guidelines. Other
suitable clock layouts may exist and it would be recommended
that the board designers simulate to guarantee compatibility
across all printed circuit and clock component process varia-
tions.
V
CC - 2V
50
Ω
50
Ω
RTT
Z
o = 50Ω
Z
o = 50Ω
FOUT
FIN
RTT =
Z
o
1
((V
OH + VOL) / (VCC – 2)) – 2
3.3V
125
Ω
125
Ω
84
Ω
84
Ω
Z
o = 50Ω
Z
o = 50Ω
FOUT
FIN
FREQUENCY STABILITY
The table shown provides a basic guideline in selecting
the proper quartz crystal that meets a timing budget of
±100ppm. For more information on selecting the proper
r
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Pl
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Ts
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T
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3
±
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il
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F
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±
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r
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g
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1
±m
p
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o
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A
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L3
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E
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T
l
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v
O
l
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o
T
8
±m
p
crystal, see the application note, Crystal Timing Budget
and Accuracy for FemtoClock .
相关PDF资料
PDF描述
ICS843AG-75LF 75 MHz, OTHER CLOCK GENERATOR, PDSO8
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