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| 型号： | ICS844003CG-01LFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 680 MHz, OTHER CLOCK GENERATOR, PDSO24 |
| 封装： | 4.40 X 7.80 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-24 |
| 文件页数： | 1/15页 |
| 文件大小： | 663K |
| 代理商： | ICS844003CG-01LFT |
FEMTOCLOCKS CRYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
ICS844003-01
IDT / ICS LVDS FREQUENCY SYNTHESIZER
1
ICS844003CG-01 REV A OCTOBER 31, 2006
PRELIMINARY
GENERAL DESCRIPTION
The ICS844003-01 is a 3 differential output LVDS
Synthesizer designed to generate Ethernet reference
clock frequencies and is a member of the
HiPerClocks family of high performance clock
solutions from IDT. Using a 19.53125MHz or 25MHz,
18pF parallel resonant crystal, the following frequencies can be
generated based on the settings of 4 frequency select pins
(DIV_SEL[A1:A0], DIV_SEL[B1:B0]): 625MHz, 312.5MHz,
156.25MHz, and 125MHz. The 844003-01 has 2 output banks,
Bank A with 1 differential LVDS output pair and Bank B with 2
differential LVDS output pairs.
The two banks have their own dedicated frequency select pins
and can be independently set for the frequencies mentioned
above. The ICS844003-01 uses IDT’s 3rd generation low phase
noise VCO technology and can achieve 1ps or lower typical rms
phase jitter, easily meeting Ethernet jitter requirements. The
ICS844003-01 is packaged in a small 24-pin TSSOP package.
FEATURES
Three LVDS outputs on two banks, Bank A with one LVDS
pair and Bank B with 2 LVDS output pairs
Using a 19.53125MHz or 25MHz crystal, the two output
banks can be independently set for 625MHz, 312.5MHz,
156.25MHz or 125MHz
Selectable crystal oscillator interface or LVCMOS/LVTTL
single-ended input
VCO range: 490MHz to 680MHz
RMS phase jitter @ 156.25MHz (1.875MHz - 20MHz):
0.56ps (typical)
3.3V output supply mode
0°C to 70°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
HiPerClockS
ICS
0
1
0
1
Phase
Detector
VCO
0 = ÷25 (default)
1 = ÷32
0 0
÷1
0 1
÷2
1 0
÷3
1 1
÷4 (default)
0 0
÷2
0 1
÷4
1 0
÷5
1 1
÷8 (default)
FB_DIV
OSC
QA0
nQA0
QB0
nQB0
QB1
nQB1
CLK_ENA
CLK_ENB
MR
DIV_SELA[1:0]
DIV_SELB[1:0]
VCO_SEL
XTAL_SEL
FB_DIV
TEST_CLK
XTAL_IN
XTAL_OUT
Pulldown
Pullup
BLOCK DIAGRAM
PIN ASSIGNMENT
ICS844003-01
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
DIV_SELB0
VCO_SEL
MR
VDDO_A
QA0
nQA0
OEB
OEA
FB_DIV
VDDA
VDD
DIV_SELA0
1
2
3
4
5
6
7
8
9
10
11
12
DIV_SELB1
VDDO_B
QB0
nQB0
QB1
nQB1
XTAL_SEL
REF_CLK
XTAL_IN
XTAL_OUT
GND
DIV_SELA1
24
23
22
21
20
19
18
17
16
15
14
13
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product
characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
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