参数资料
型号: ICS844020AY-45
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟产生/分配
英文描述: 156.25 MHz, OTHER CLOCK GENERATOR, PQFP64
封装: 10 X 10 MM, 1 MM HEIGHT, TQFP-64
文件页数: 13/13页
文件大小: 602K
代理商: ICS844020AY-45
IDT / ICS LVDS/LVCMOS FREQUENCY SYNTHESIZER
9
ICS844020-45 REV A JUNE 14, 2006
ICS844020-45
FEMTOCLOCK CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
PRELIMINARY
OUTPUTS:
LVCMOS OUTPUT:
All unused LVCMOS output can be left floating. There should
be no trace attached.
LVDS OUTPUT
All unused LVDS output pairs can be either left floating or
terminated with 100
across. If they are left floating, there
should be no trace attached.
RECOMMENDATIONS FOR UNUSED OUTPUT PINS
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS
signal through an AC couple capacitor. A general interface diagram
is
shown
in
Figure
3.
The
XTAL_OUT
pin
can
be left floating. The input edge rate can be as slow as
10ns. For LVCMOS inputs, it is recommended that the
amplitude be reduced from full swing to half swing in order
to prevent signal interference with the power rail and to
reduce noise. This configuration requires that the output
Figure 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
impedance of the dr iver (Ro) plus the series resistance
(Rs) equals the transmission line impedance. In addition, matched
termination at the crystal input will attenuate the signal in half.
This can be done in one of two ways. First, R1 and R2 in parallel
should equal the transmission line impedance. For most 50
applications, R1 and R2 can be 100
. This can also be
accomplished by removing R1 and making R2 50
.
R2
Zo = 50
VDD
Ro
Zo = Ro + Rs
R1
VDD
XTAL_IN
XTAL_OUT
.1uf
Rs
相关PDF资料
PDF描述
ICS844020AY-45T 156.25 MHz, OTHER CLOCK GENERATOR, PQFP64
ICS844020AY-45LF 156.25 MHz, OTHER CLOCK GENERATOR, PQFP64
ICS844021AG-01LF 170 MHz, OTHER CLOCK GENERATOR, PDSO8
ICS8440258AKI-46T 125 MHz, OTHER CLOCK GENERATOR, QCC32
ICS8440258AKI-46LTF 125 MHz, OTHER CLOCK GENERATOR, QCC32
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