参数资料
型号: ICS844031BGI-01LF
厂商: IDT, Integrated Device Technology Inc
文件页数: 12/13页
文件大小: 0K
描述: IC CLK GEN ETHERNET 8TSSOP
标准包装: 96
系列: HiPerClockS™, FemtoClock™
类型: 时钟发生器
PLL:
输入: 晶体
输出: LVDS
电路数: 1
比率 - 输入:输出: 1:1
差分 - 输入:输出: 无/是
频率 - 最大: 340MHz
除法器/乘法器: 是/无
电源电压: 2.375 V ~ 3.465 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 8-TSSOP
包装: 管件
IDT / ICS LVDS CLOCK GENERATOR
8
ICS844031BGI-01 REV. A MAY 1, 2008
ICS844031I-01
FEMTOCLOCKS CRYSTAL-TO-LVDS CLOCK GENERATOR
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in
Figure 3. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to
half swing in order to prevent signal interference with the power
rail and to reduce noise. This configuration requires that the output
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50
Ω applications, R1
and R2 can be 100
Ω.This can also be accomplished by removing
R1 and making R2 50
Ω.
R2
Zo = 50
VDD
Ro
Zo = Ro + Rs
R1
VDD
XTAL_IN
XTAL_OUT
.1uf
Rs
3.3V, 2.5V LVDS DRIVER TERMINATION
A general LVDS interface is shown in
Figure 4 In a 100
Ω
differential transmission line environment, LVDS drivers
require a matched load termination of 100
Ω across near
FIGURE 4. TYPICAL LVDS DRIVER TERMINATION
the receiver input. For a multiple LVDS outputs buffer, if only
partial outputs are used, it is recommended to terminate the
unused outputs.
R1
100
3.3V or 2.5V
100
Ω Differential Transmission
VDD
+
-
LVDS
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