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| 型号： | ICS844101AGI-312LF |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 312.5 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| 封装： | 4.40 X 5 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-16 |
| 文件页数： | 6/13页 |
| 文件大小： | 170K |
| 代理商： | ICS844101AGI-312LF |
844101AGI-312
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 28, 2005
2
Integrated
Circuit
Systems, Inc.
ICS844101I-312
FEMTOCLOCKS CRYSTAL-TO-LVDS
312.5MHZ FREQUENCY MARGINING SYNTHESIZER
PRELIMINARY
FUNCTIONAL DESCRIPTION
The ICS844101I-312 features a fully integrated PLL and
therefore requires no external components for setting the
loop bandwidth. A 25MHz fundamental crystal is used as
the input to the on chip oscillator. The output of the oscilla-
tor is fed into the pre-divider. In frequency margining mode,
the 25MHz crystal frequency is divided by 2 and a 12.5MHz
reference frequency is applied to the phase detector. The
VCO of the PLL operates over a range of 560MHz to
690MHz. The output of the M divider is also applied to the
phase detector.
The default mode for the ICS844101I-312 is 312.5MHz
output frequency using a 25MHz crystal. The output fre-
quency can be changed by placing the device into the
margining mode using the mode pin and using the serial
interface to program the M feedback divider. Frequency
margining mode operation occurs when the MODE input
is HIGH. The phase detector and the M divider force the
VCO output frequency to be M times the reference fre-
quency by adjusting the VCO control voltage. Note that for
some values of M (either too high or too low), the PLL will
not achieve lock. The output of the VCO is scaled by an
output divider prior to being sent to the LVPECL output
buffer. The divider provides a 50% output duty cycle. The
relationship between the crystal input frequency, the M
divider, the VCO frequency and the output frequency is
provided in Table 1. When changing back from frequency
margining mode to nominal mode, the device will return to
the default nominal configuration that will provide
312.5MHz output frequency.
Serial operation occurs when S_LOAD is HIGH. Serial data
can be loaded in either the default mode or the frequency
margining mode. The 6-bit shift register is loaded by sam-
pling the S_DATA bits with the rising edge of S_CLOCK.
After shifting in the 6-bit M divider value, S_LOAD is
transitioned from HIGH to LOW which latches the contents of
the shift-register into the M divider control register. When
S_LOAD is LOW, any transitions of S_CLOCK or S_DATA
are ignored.
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TABLE 1. FREQUENCY MARGIN FUNCTION TABLE
FIGURE 1. SERIAL LOAD OPERATIONS
Time
SERIAL LOADING
t
S
t
H
M5
M4
M3
M2
M1
M0
t
S
S_CLOCK
S_DATA
S_LOAD
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