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| 型号： | ICS85301AKLF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 85301 SERIES, LOW SKEW CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC16 |
| 封装： | 3 X 3 MM, 0.95 MM HEIGHT, ROHS COMPLIANT, MO-220, VFQFN-16 |
| 文件页数： | 16/20页 |
| 文件大小： | 725K |
| 代理商： | ICS85301AKLF |
IDT / ICS 2:1, LVPECL MULTIPLEXER
5
ICS85301 REV. B DECEMBER 22, 2006
ICS85301
2:1, DIFFERENTIAL-TO-LVPECL MULTIPLEXER
ADDITIVE PHASE JITTER
Additive Phase Jitter
3.3V or 2.5V @ 622MHz (12kHz to 20MHz)
= 0.009ps typical
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
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-120
-130
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-190
1k
10k
100k
1M
10M
100M
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The device
band to the power in the fundamental. When the required offset
is specified, the phase noise is called a
dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
meets the noise floor of what is shown, but can actually be lower.
The phase noise is dependant on the input source and
measurement equipment.
OFFSET FROM CARRIER FREQUENCY (HZ)
SSB
P
HASE
N
OISE
dB
c
/H
Z
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