- 您现在的位置：买卖IC网 > PDF目录2073 > ICS85310AYI-01LFT (IDT, Integrated Device Technology Inc)IC CLOCK BUFFER MUX 2:10 32-LQFP PDF资料下载
参数资料
| 型号： | ICS85310AYI-01LFT |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 14/18页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK BUFFER MUX 2:10 32-LQFP |
| 标准包装： | 1,000 |
| 系列： | HiPerClockS™ |
| 类型： | 扇出缓冲器（分配），多路复用器 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:10 |
| 差分 - 输入:输出： | 是/是 |
| 输入： | HCSL，LVDS，LVHSTL，LVPECL，SSTL |
| 输出： | ECL，LVPECL |
| 频率 - 最大： | 700MHz |
| 电源电压： | 2.375 V ~ 3.8 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP |
| 供应商设备封装： | 32-TQFP（7x7） |
| 包装： | 带卷 (TR) |
| 其它名称： | 85310AYI-01LFT |
ICS85310AYI-01 REVISION I JANUARY 25, 2010
5
2010 Integrated Device Technology, Inc.
ICS5310I-01 Data Sheet
LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL/ECL FANOUT BUFFER
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
Additive Phase Jitter, RMS
@ 155.52MHz = <0.13ps (typical)
SSB
Phas
e
N
o
ise
dBc/Hz
Offset from Carrier Frequency (Hz)
相关PDF资料 |
PDF描述 |
|---|---|
| ICS85310AYI-11LF | IC CLOCK BUFFER MUX 2:10 32-LQFP |
| ICS85310AYI-21LN | IC CLK BUFFER 1:5 700MHZ 32-LQFP |
| ICS85311AMILF | IC CLOCK BUFFER 1:2 1GHZ 8-SOIC |
| ICS85311AMLF | IC CLOCK BUFFER 1:2 1GHZ 8-SOIC |
| ICS85314BMI-01LF | IC CLOCK BUFFER MUX 2:5 20-SOIC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS85310AYI-01LN | 制造商:INT_CIR_SYS 功能描述: |
| ICS85310AYI-11LF | 功能描述:IC CLOCK BUFFER MUX 2:10 32-LQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟缓冲器，驱动器 系列:HiPerClockS™ 标准包装:74 系列:- 类型:扇出缓冲器（分配） 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 输入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 输出:HCSL，LVDS 频率 - 最大:400MHz 电源电压:3 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:管件 |
| ICS85310AYI-11LFT | 功能描述:IC CLOCK BUFFER MUX 2:10 32-LQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟缓冲器，驱动器 系列:HiPerClockS™ 标准包装:74 系列:- 类型:扇出缓冲器（分配） 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 输入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 输出:HCSL，LVDS 频率 - 最大:400MHz 电源电压:3 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:管件 |
| ICS85310AYI-21 | 制造商:INT_CIR_SYS 功能描述: |
| ICS85310AYI-21LN | 功能描述:IC CLK BUFFER 1:5 700MHZ 32-LQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟缓冲器，驱动器 系列:HiPerClockS™ 标准包装:74 系列:- 类型:扇出缓冲器（分配） 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 输入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 输出:HCSL，LVDS 频率 - 最大:400MHz 电源电压:3 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:管件 |
发布紧急采购，3分钟左右您将得到回复。