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| 型号： | ICS853111Y |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封装： | 7 X 7 MM, 1.40 MM HEIGHT, LQFP-32 |
| 文件页数： | 10/12页 |
| 文件大小： | 161K |
| 代理商： | ICS853111Y |
853111AY
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 14, 2002
7
Integrated
Circuit
Systems, Inc.
ICS853111
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
PRELIMINARY
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
F
OUT
F
IN
5
2 Zo
Z
o
5
2
Z
o
3
2
Z
o
3
2
Z
o = 50
Z
o = 50
RTT =
1
(V
OH + VOL / VCC –2) –2
Z
o
Z
o = 50
Z
o = 50
50
50
RTT
V
CC - 2V
F
IN
F
OUT
50
transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion.
Figures 3A and 3B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FIGURE 3B. LVPECL OUTPUT TERMINATION
FIGURE 3A. LVPECL OUTPUT TERMINATION
Figure 2 shows an example of the differential input that can
be wired to accept single ended levels. The reference voltage
level V
BB generated from the device is connected to the
CLK_IN
C1
0.1uF
VDD(or VCC)
+
-
VBB
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
negative input. The C1 capacitor should be located as close
as possible to the input pin.
TERMINATION FOR LVPECL OUTPUTS
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS85311AMI | 制造商:Integrated Device Technology Inc 功能描述:IC CLK BUFFER 1:2 1GHZ 8SOIC |
| ICS85311AMILF | 功能描述:IC CLOCK BUFFER 1:2 1GHZ 8-SOIC RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟缓冲器，驱动器 系列:HiPerClockS™ 标准包装:74 系列:- 类型:扇出缓冲器（分配） 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 输入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 输出:HCSL，LVDS 频率 - 最大:400MHz 电源电压:3 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:管件 |
| ICS85311AMILFT | 功能描述:IC CLOCK BUFFER 1:2 1GHZ 8-SOIC RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟缓冲器，驱动器 系列:HiPerClockS™ 标准包装:74 系列:- 类型:扇出缓冲器（分配） 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 输入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 输出:HCSL，LVDS 频率 - 最大:400MHz 电源电压:3 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:管件 |
| ICS85311AMIT | 制造商:Integrated Device Technology Inc 功能描述:IC CLK BUFFER 1:2 1GHZ 8SOIC |
| ICS85311AMLF | 功能描述:IC CLOCK BUFFER 1:2 1GHZ 8-SOIC RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟缓冲器，驱动器 系列:HiPerClockS™ 标准包装:74 系列:- 类型:扇出缓冲器（分配） 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 输入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 输出:HCSL，LVDS 频率 - 最大:400MHz 电源电压:3 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:管件 |
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