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| 型号： | ICS8531AY-01 |
| 元件分类： | 时钟及定时 |
| 英文描述： | LOW SKEW CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封装： | 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32 |
| 文件页数： | 13/15页 |
| 文件大小： | 285K |
| 代理商： | ICS8531AY-01 |
8531AY-01
www.icst.com/products/hiperclocks.html
REV. C FEBRUARY 2, 2004
7
Integrated
Circuit
Systems, Inc.
ICS8531-01
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
APPLICATION INFORMATION
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF ~ V
CC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs.Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
drive 50
transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion.
Figures 3A and 3B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
TERMINATION FOR LVPECL OUTPUTS
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
V
CC - 2V
50
50
RTT
Z
o = 50
Z
o = 50
FOUT
FIN
RTT =
Z
o
1
((V
OH + VOL) / (VCC – 2)) – 2
3.3V
125
125
84
84
Z
o = 50
Z
o = 50
FOUT
FIN
FIGURE 3B. LVPECL OUTPUT TERMINATION
FIGURE 3A. LVPECL OUTPUT TERMINATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
CC = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
R2
1K
V
CC
CLK_IN
+
-
R1
1K
C1
0.1uF
V_REF
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