参数资料
型号: ICS8535AGI-11LF
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟及定时
英文描述: LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 4 INVERTED OUTPUT(S), PDSO20
封装: 6.50 X 4.40 MM, 0.92 MM HEIGHT, MO-153, TSSOP-20
文件页数: 12/14页
文件大小: 134K
代理商: ICS8535AGI-11LF
8535AGI-11
www.icst.com/products/hiperclocks.html
REV. C JANUARY 16, 2003
7
Integrated
Circuit
Systems, Inc.
ICS8535I-11
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/
LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
APPLICATION INFORMATION
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
F
OUT
F
IN
5
2 Zo
Z
o
5
2
Z
o
3
2
Z
o
3
2
Z
o = 50
Z
o = 50
RTT =
1
(V
OH + VOL / VCC –2) –2
Z
o
Z
o = 50
Z
o = 50
50
50
RTT
V
CC - 2V
F
IN
F
OUT
50
transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion.
Figures 2A and 2B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
TERMINATION FOR LVPECL OUTPUTS
FIGURE 2B. LVPECL OUTPUT TERMINATION
FIGURE 2A. LVPECL OUTPUT TERMINATION
相关PDF资料
PDF描述
ICS8535AGI-11 LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 4 INVERTED OUTPUT(S), PDSO20
ICS8535AGI-31 266 MHz, OTHER CLOCK GENERATOR, PDSO20
ICS8535BGI-01LF 8535 SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
ICS8535BKI-01 8535 SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 4 INVERTED OUTPUT(S), QCC20
ICS8535BKI-01LF 8535 SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 4 INVERTED OUTPUT(S), QCC20
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