参数资料
型号: ICS85408BGLFT
厂商: IDT, Integrated Device Technology Inc
文件页数: 13/16页
文件大小: 0K
描述: IC CLK BUFF 1:8 700MHZ 24-TSSOP
标准包装: 2,500
系列: HiPerClockS™
类型: 扇出缓冲器(分配)
电路数: 1
比率 - 输入:输出: 1:8
差分 - 输入:输出: 是/是
输入: HCSL,LVDS,LVHSTL,LVPECL,SSTL
输出: LVDS
频率 - 最大: 700MHz
电源电压: 3.135 V ~ 3.465 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 24-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 24-TSSOP
包装: 带卷 (TR)
其它名称: 85408BGLFT
ICS85408 Datasheet
LOW SKEW, 1-TO-8, DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
ICS85408BG REVISION B JUNE 25, 2009
6
2009 Integrated Device Technology, Inc.
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
SSB
Phas
e
Noise
dBc/Hz
Offset from Carrier Frequency (Hz)
Additive Phase Jitter @156.25MHz
12kHz – 20MHz = 167fs (typical)
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