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| 型号： | ICS8545BGLF |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 8/10页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK BUFFER MUX 2:4 20-TSSOP |
| 标准包装： | 74 |
| 系列： | HiPerClockS™ |
| 类型： | 扇出缓冲器（分配），多路复用器 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:4 |
| 差分 - 输入:输出： | 无/是 |
| 输入： | LVCMOS，LVTTL |
| 输出： | LVDS |
| 频率 - 最大： | 650MHz |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 20-TSSOP |
| 包装： | 管件 |
| 其它名称： | 8545BGLF ICS8545BGLF-ND |
2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FMS6203 Rev. 1.0.4
6
FM
S6203
—
Low-
C
ost
,3-
C
h
annel,
Video
Filt
er
D
river
f
o
rSD
/PS/H
D
Layout Considerations
General layout and supply bypassing play a major role
in
high-frequency
performance
and
thermal
characteristics. Fairchild offers an evaluation board to
guide layout and aid device evaluation. The evaluation
board is a four-layer board with full power and ground
planes. Following this layout configuration provides
optimum performance and thermal characteristics for
the device. For the best results, follow the steps and
recommended routing rules listed below.
Recommended Routing / Layout Rules
Do not run analog and digital signals in parallel.
Use separate analog and digital power planes to
supply power.
Run traces on top of the ground plane at all times.
Do not run traces over ground/power splits.
Avoid routing at 90-degree angles.
Minimize clock and video data trace length
differences.
Include 10F and 0.1F ceramic power supply
bypass capacitors.
Place the 0.1F capacitor within 0.1 inches of the
device power pin.
Place the 10F capacitor within 0.75 inches of the
device power pin.
For multi-layer boards, use a large ground plane to
help dissipate heat.
For two-layer boards, use a ground plane that
extends beyond the device body by at least 0.5
inches on all sides. Include a metal paddle under
the device on the top layer.
Minimize all trace lengths to reduce series
inductance.
Thermal Considerations
Since the interior of most systems, such as set-top
boxes, TVs, and DVD players, are at +70C;
consideration must be given to providing an adequate
heat sink for the device package for maximum heat
dissipation. When designing a system board, determine
how much power each device dissipates. Ensure that
devices of high power are not placed in the same
location, such as directly above (top plane) and below
bottom plane) each other on the PCB.
PCB Thermal Layout Considerations
Understand the system power requirements and
environmental conditions.
Maximize thermal performance of the PCB.
Consider 70m copper for high-power designs.
Make the PCB as thin as possible by reducing FR4
thickness.
Use vias in the power pad to tie adjacent layers
together.
Remember that baseline temperature is a function
of board area, not copper thickness.
Use modeling techniques for first-order
approximation.
Output Considerations
The FMS6203 outputs are DC offset from the input by
150mV; therefore, VOUT = 2VIN DC+150mV. This offset
is required to obtain optimal performance from the
output driver and is held at the minimum value to
decrease the standing DC current into the load. Since
the FMS6203 has a 2x (6dB) gain, the output is typically
connected via a 75-series back-matching resistor
followed by the 75 video cable. Because of the
inherent divide by two of this configuration, the blanking
level at the load of the video signal is always less than
1V. When AC-coupling the output, ensure that the
coupling capacitor of choice passes the lowest
frequency content in the video signal and that line time
distortion (video tilt) is kept as low as possible.
The selection of the coupling capacitor is a function of
the subsequent circuit input impedance and the leakage
current of the input being driven. To obtain the highest
quality output video signal, the series termination
resistor must be placed as close to the device output
pin as possible. This greatly reduces the parasitic
capacitance and inductance effect on the FMS6203
output driver. Recommended distance from device pin
to place series termination resistor is no greater than
0.1 inches.
Figure 3.
Distance from Device Pin to Series
Termination Resistor
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