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参数资料
| 型号： | ICS8701CYT |
| 元件分类： | 时钟及定时 |
| 英文描述： | 8701 SERIES, LOW SKEW CLOCK DRIVER, 20 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48 |
| 封装： | 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-48 |
| 文件页数： | 1/12页 |
| 文件大小： | 258K |
| 代理商： | ICS8701CYT |
8701CY
www.icst.com/products/hiperclocks.html
REV. D FEBRUARY 27, 2006
1
Integrated
Circuit
Systems, Inc.
ICS8701
LOW SKEW,
÷1, ÷2
LVCMOS/LVTTL CLOCK GENERATOR
GENERAL DESCRIPTION
The ICS8701 is a low skew, ÷1, ÷2 LVCMOS/
LVTTL Clock Generator and a member of the
HiPerClockSfamily of High Performance Clock
Solutions from ICS. The low impedance LVCMOS
outputs are designed to drive 50
Ω series or
parallel terminated transmission lines. The effective fanout can
be increased from 20 to 40 by utilizing the ability of the out-
puts to drive two series terminated lines.
The divide select inputs, DIV_SELx, control the output fre-
quency of each bank. The outputs can be utilized in the ÷1,
÷2 or a combination of ÷1 and ÷2 modes. The bank enable
inputs, BANK_EN0:1, support enabling and disabling each
bank of outputs individually. The master reset input, nMR/
OE, resets the internal frequency dividers and also con-
trols the active and high impedance states of all outputs.
The ICS8701 is characterized at 3.3V and mixed 3.3V input
supply, and 2.5V output supply operating modes. Guaranteed
bank, output and part-to-part skew characteristics make the
ICS8701 ideal for those clock distribution applications de-
manding well defined performance and repeatability.
FEATURES
Twen
ty LVCMOS outputs, 7
Ω typical output impedance
One LVCMOS/LVTTL clock input
Maximum output frequency: 250MHz
Bank enable logic allows unused banks to be disabled
in reduced fanout applications
Output skew: 250ps (maximum)
Part-to-part skew: 600ps (maximum)
Bank skew: 200ps (maximum)
Multiple frequency skew: 300ps (maximum)
3.3V or mixed 3.3V input, 2.5V output operating
supply modes
0°C to 70°C ambient operating temperature
Other divide values available on request
Available in both standard and lead-free RoHS compliant
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
nMR/OE
BANK_EN0
BANK_EN1
QA0:QA4
QB0:QB4
QC0:QC4
QD0:QD4
CLK
48 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
QC3
VDDO
QC4
QD0
VDDO
QD1
GND
QD2
GND
QD3
VDDO
QD4
QB1
VDDO
QB0
QA4
VDDO
QA3
GND
QA2
GND
QA1
VDDO
QA0
DIV_SELA
DIV_SELB
CLK
GND
V
DD
BANK_EN0
GND
BANK_EN1
V
DD
nMR/OE
DIV_SELC
DIV_SELD
GND
QB2
GND
QB3
V
DDO
QB4
QC0
V
DDO
QC1
GND
QC2
GND
48-Pin LQFP
7mm x 7mm x 1.4mm
Y Package
Top View
ICS8701
HiPerClockS
ICS
1
0
÷1
÷2
1
0
1
0
1
0
Bank Enable
Logic
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相关代理商/技术参数 |
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