参数资料
型号: ICS8725AY-01T
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟及定时
英文描述: 8725 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
封装: 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32
文件页数: 1/16页
文件大小: 229K
代理商: ICS8725AY-01T
8725AY-01
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 15, 2005
1
Integrated
Circuit
Systems, Inc.
ICS8725-01
1:5 DIFFERENTIAL-TO-HSTL
ZERO DELAY CLOCK GENERATOR
GENERAL DESCRIPTION
The ICS8725-01 is a highly versatile 1:5 Dif-
ferential-to-HSTL clock generator and a
member of the HiPerClockS family of High
Performance Clock Solutions from ICS. The
ICS8725-01 has a fully integrated PLL and can
be configured as zero delay buffer, multiplier or divider,
and has an output frequency range of 31.25MHz to
700MHz. The reference divider, feedback divider and out-
put divider are each programmable, thereby allowing for
the following output-to-input frequency ratios: 8:1, 4:1, 2:1,
1:1, 1:2, 1:4, 1:8. The external feedback allows the device
to achieve “zero delay” between the input clock and the
output clocks. The PLL_SEL pin can be used to bypass the
PLL for system test and debug purposes. In bypass mode,
the reference clock is routed around the PLL and into the
internal output dividers.
BLOCK DIAGRAM
PIN ASSIGNMENT
FEATURES
Five differential HSTL outputs
Selectable differential CLKx, nCLKx input pairs
CLKx, nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, HSTL, SSTL, HCSL
Output frequency range: 31.25MHz to 700MHz
Input frequency range: 31.25MHz to 700MHz
VCO range: 250MHz to 700MHz
External feedback for “zero delay” clock regeneration
with configurable frequencies
Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
Static phase offset: ±100ps
Cycle-to-cycle jitter: 25ps
Output skew: 25ps
3.3V core, 1.8V output operating supply
0°C to 70°C ambient operating temperature
Available in both standard and lead-free RoHS-compliant
packages
HiPerClockS
ICS
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
32 31 30 29 28 27 26 25
9
10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
VDDO
Q3
nQ3
Q2
nQ2
Q1
nQ1
VDDO
SEL0
SEL1
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
MR
V
DDO
Q0
nQ0
GND
SEL2
FB_IN
nFB_IN
V
DD
V
DDO
nQ4
Q4
GND
SEL3
V
DDA
PLL_SEL
V
DD
ICS8725-01
PLL_SEL
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
FB_IN
nFB_IN
SEL0
SEL1
SEL2
SEL3
MR
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
0
1
PLL
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
0
1
÷1, ÷2, ÷4, ÷8,
÷16, ÷32, ÷64
相关PDF资料
PDF描述
ICS8725AYI-01LF 8725 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
ICS873032AMLF 873032 SERIES, LOW SKEW CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
ICS873032AGLF 873032 SERIES, LOW SKEW CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
ICS873032AMLFT 873032 SERIES, LOW SKEW CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
ICS873032AM 873032 SERIES, LOW SKEW CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
相关代理商/技术参数
参数描述
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