参数资料
型号: ICS874005AGLF
元件分类: 时钟及定时
英文描述: 874005 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24
封装: 4.40 X 7.80 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-24
文件页数: 9/12页
文件大小: 462K
代理商: ICS874005AGLF
Integrated
Circuit
Systems, Inc.
874005AG
www.icst.com/products/hiperclocks.html
REV. A JANUARY 25, 2006
6
ICS874005
PCI EXPRESS
JITTER ATTENUATOR
APPLICATION INFORMATION
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
DD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
DD = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
V_REF
R1
1K
C1
0.1u
R2
1K
Single Ended Clock Input
CLK
nCLK
VDD
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS874005 provides sepa-
rate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
DD, VDDA, and VDDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10
Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each V
CCA pin.
FIGURE 1. POWER SUPPLY FILTERING
10
Ω
V
DDA
10
μF
.01
μF
3.3V
.01
μF
V
DD
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