参数资料
型号: ICS874005AGT
元件分类: 时钟及定时
英文描述: 874005 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24
封装: 4.40 X 7.80 MM, 0.92 MM HEIGHT, MO-153, TSSOP-24
文件页数: 12/12页
文件大小: 462K
代理商: ICS874005AGT
Integrated
Circuit
Systems, Inc.
874005AG
www.icst.com/products/hiperclocks.html
REV. A JANUARY 25, 2006
9
ICS874005
PCI EXPRESS
JITTER ATTENUATOR
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS874005.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS874005 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
DD = 3.3V + 5% = 3.465V, which gives worst case results.
Power (core)
MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (85mA + 15mA) = 346.5mW
Power (outputs)
MAX = VDDO_MAX * IDDO_MAX = 3.465V * 115mA = 398.48mW
Total Power
_MAX = 346.5mW + 398.48mW = 745mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of
the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj =
θ
JA * Pd_total + TA
Tj = Junction Temperature
q
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
θ
JA must be used.
Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 63°C/W per
Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.745W * 63°C/W = 117°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air
flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE
θθθθθ
JA
FOR
24-LEAD TSSOP, FORCED CONVECTION
θθθθθ
JA by Velocity (Linear Feet per Minute)
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
70°C/W
63°C/W
60°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
相关PDF资料
PDF描述
ICS874005AG 874005 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24
ICS874005AGLF 874005 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24
ICS8741004AGIT 8741004 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24
ICS8741004AGI 8741004 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24
ICS8741004AGI 8741004 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24
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