参数资料
型号: ICS87421AMILFT
厂商: IDT, Integrated Device Technology Inc
文件页数: 10/14页
文件大小: 0K
描述: IC CLOCK GEN LVDS 8-SOIC
标准包装: 2,500
系列: HiPerClockS™
类型: 时钟发生器
PLL:
输入: HCSL,LVDS,LVHSTL,LVPECL,SSTL
输出: LVDS
电路数: 1
比率 - 输入:输出: 1:1
差分 - 输入:输出: 是/是
频率 - 最大: 1GHz
除法器/乘法器: 是/无
电源电压: 3.135 V ~ 3.465 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 带卷 (TR)
其它名称: 87421AMILFT
IDT / ICS LVDS CLOCK GENERATOR
5
ICS87421AMI REV. A OCTOBER 3, 2007
ICS87421I
÷1/÷2 DIFFERENTIAL-TO-LVDS CLOCK GENERATOR
ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The device
band to the power in the fundamental. When the required offset
is specified, the phase noise is called a dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
meets the noise floor of what is shown, but can actually be lower.
The phase noise is dependant on the input source and
measurement equipment.
OFFSET FROM CARRIER FREQUENCY (HZ)
SSB
P
HASE
N
OISE
dB
c
/H
Z
Additive Phase Jitter @
155.52MHz (12kHz to 20MHz) = 0.17ps typical
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