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| 型号： | ICS8745BYI |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 8745 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封装： | 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32 |
| 文件页数： | 1/20页 |
| 文件大小： | 1383K |
| 代理商： | ICS8745BYI |
1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY
CLOCK GENERATOR
ICS8745BI
IDT / ICS LVDS ZERO DELAY CLOCK GENERATOR
1
ICS8745BYIREV. C APRIL 16, 2007
Description
The ICS8745BI is a highly versatile 1:5 LVDS Clock
Generator and a member of the HiPerClockSf
family of High Performance Clock Solutions from
IDT. The ICS8745BI has a fully integrated PLL and
can be configured as zero delay buffer, multiplier or
divider, and has an output frequency range of 31.25MHz to
700MHz. The Reference Divider, Feedback Divider and Output
Divider are each programmable, thereby allowing for the following
output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8.
The external feedback allows the device to achieve “zero delay”
between the input clock and the output clocks. The PLL_SEL pin
can be used to bypass the PLL for system test and debug
purposes. In bypass mode, the reference clock is routed around
the PLL and into the internal output dividers.
Features
Five differential LVDS outputs designed to meet
or exceed the requirements of ANSI TIA/EIA-644
Selectable differential clock inputs
CLKx, CLKx pairs can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
Output frequency range: 31.25MHz to 700MHz
Input frequency range: 31.25MHz to 700MHz
VCO range: 250MHz to 700MHz
External feedback for “zero delay” clock regeneration
with configurable frequencies
Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
Cycle-to-cycle jitter: 30ps (maximum)
Output skew: 40ps (maximum)
Static phase offset: 25ps ± 125ps
Full 3.3V supply voltage
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
HiPerClockS
ICS
ICS8745BI
32-Lead LQFP
7mm x 7mm x 1.4mm
package body
Block Diagram
PLL_SEL
CLK0
CLK1
CLK_SEL
FB_IN
SEL0
SEL1
SEL2
SEL3
MR
Q0
Q1
Q2
Q3
Q4
0
1
PLL
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
0
1
÷1, ÷2, ÷4, ÷8,
÷16, ÷32, ÷64
Pullup
Pulldown
Pullup
Pulldown
Pullup
Pulldown
Pullup
Pulldown
Pin Assignment
9
10 11 12 13 14 15 16
32 31 30
29 28
27 26 25
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
SEL0
SEL1
CLK0
CLK1
CLK_SEL
MR
Q3
VDDO
Q2
GND
Q1
V
DD
FB_IN
SEL2
GND
Q0
V
DDO
PLL_SEL
V
DDA
SEL3
V
DDO
Q4
GND
V
DD
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS8745BYILF | 功能描述:IC CLK GEN 5LVDS 32-LQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:HiPerClockS™ 标准包装:2,000 系列:- 类型:PLL 频率合成器 PLL:是 输入:晶体 输出:时钟 电路数:1 比率 - 输入:输出:1:1 差分 - 输入:输出:无/无 频率 - 最大:1GHz 除法器/乘法器:是/无 电源电压:4.5 V ~ 5.5 V 工作温度:-20°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-LSSOP（0.175"，4.40mm 宽） 供应商设备封装:16-SSOP 包装:带卷 (TR) 其它名称:NJW1504V-TE1-NDNJW1504V-TE1TR |
| ICS8745BYILFT | 功能描述:IC CLK GEN 1:5 DIFF-LVDS 32-LQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:HiPerClockS™ 标准包装:27 系列:Precision Edge® 类型:频率合成器 PLL:是 输入:PECL，晶体 输出:PECL 电路数:1 比率 - 输入:输出:1:1 差分 - 输入:输出:无/是 频率 - 最大:800MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 5.25 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:28-SOIC（0.295"，7.50mm 宽） 供应商设备封装:28-SOIC 包装:管件 |
| ICS8745BYLF | 功能描述:IC CLK GEN 5LVDS 32-LQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:HiPerClockS™ 标准包装:2,000 系列:- 类型:PLL 频率合成器 PLL:是 输入:晶体 输出:时钟 电路数:1 比率 - 输入:输出:1:1 差分 - 输入:输出:无/无 频率 - 最大:1GHz 除法器/乘法器:是/无 电源电压:4.5 V ~ 5.5 V 工作温度:-20°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-LSSOP（0.175"，4.40mm 宽） 供应商设备封装:16-SSOP 包装:带卷 (TR) 其它名称:NJW1504V-TE1-NDNJW1504V-TE1TR |
| ICS8745BYLFT | 功能描述:IC CLK GEN 1:5 DIFF-LVDS 32-LQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:HiPerClockS™ 标准包装:1,000 系列:- 类型:时钟/频率合成器，扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP（8x8） 包装:带卷 (TR) 其它名称:844S012AKI-01LFT |
| ICS874S02BMI | 制造商:Integrated Device Technology Inc 功能描述:IC CLK GENERATOR ZDB 20SOIC |
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