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| 型号： | ICS874S02AMI |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 874S SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 封装： | 7.50 X 12.80 MM, 2.30 MM HEIGHT, MS-013, MO-119, SOIC-20 |
| 文件页数： | 14/15页 |
| 文件大小： | 200K |
| 代理商： | ICS874S02AMI |
874S02AMI
www.icst.com/products/hiperclocks.html
REV. A APRIL 27, 2006
8
Integrated
Circuit
Systems, Inc.
ICS874S02I
1:1 DIFFERENTIAL-TO-LVDS
ZERO DELAY CLOCK GENERATOR
PRELIMINARY
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS874S02I provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
DD, VDDA, and VDDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 2 illustrates how
a 10
Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each V
DDA pin. The 10Ω
resistor can also be replaced by a ferrite bead.
POWER SUPPLY FILTERING TECHNIQUES
FIGURE 2. POWER SUPPLY FILTERING
10
Ω
V
DDA
10
μF
.01
μF
3.3V
.01
μF
V
DD
APPLICATION INFORMATION
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF ~ V
DD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
DD = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
V_REF
R1
1K
C1
0.1u
R2
1K
Single Ended Clock Input
CLK
nCLK
VDD
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS874S02BMI | 制造商:Integrated Device Technology Inc 功能描述:IC CLK GENERATOR ZDB 20SOIC |
| ICS874S02BMILF | 功能描述:IC CLK GEN 1:1 DIFF ZD 20SOIC RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:HiPerClockS™ 标准包装:27 系列:Precision Edge® 类型:频率合成器 PLL:是 输入:PECL，晶体 输出:PECL 电路数:1 比率 - 输入:输出:1:1 差分 - 输入:输出:无/是 频率 - 最大:800MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 5.25 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:28-SOIC（0.295"，7.50mm 宽） 供应商设备封装:28-SOIC 包装:管件 |
| ICS874S02BMILFT | 功能描述:IC CLK GEN 1:1 DIFF ZD 20SOIC RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:HiPerClockS™ 标准包装:1,000 系列:- 类型:时钟/频率合成器，扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP（8x8） 包装:带卷 (TR) 其它名称:844S012AKI-01LFT |
| ICS874S02BMIT | 制造商:Integrated Device Technology Inc 功能描述:IC CLK GENERATOR ZDB 20SOIC |
| ICS874S336AGLF | 功能描述:IC CLOCK MULTIPLIER LVDS 20TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:HiPerClockS™ 标准包装:27 系列:Precision Edge® 类型:频率合成器 PLL:是 输入:PECL，晶体 输出:PECL 电路数:1 比率 - 输入:输出:1:1 差分 - 输入:输出:无/是 频率 - 最大:800MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 5.25 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:28-SOIC（0.295"，7.50mm 宽） 供应商设备封装:28-SOIC 包装:管件 |
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