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参数资料
| 型号： | ICS87972DYI |
| 英文描述： | LOW SKEW, 1-TO-12 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER |
| 中文描述： | 低偏移，1至12个LVCMOS时钟倍频/零延迟缓冲器 |
| 文件页数： | 10/14页 |
| 文件大小： | 150K |
| 代理商： | ICS87972DYI |
87972DYI
www.icst.com/products/hiperclocks.html
10
REV. A OCTOBER 18, 2002
ICS87972I
L
OW
S
KEW
, 1-
TO
-12
LVCMOS C
LOCK
M
ULTIPLIER
/Z
ERO
D
ELAY
B
UFFER
F
L
F
C
Qx F
REEZE
Internal
Qx Internal
Qx Out
FRZ_CLK
FRZ_DATA
StBt
QA0
QA1
QA2
QA3
QB0
QB1
QB2
QB3
QB1
QB2
QB3
QSYNC
A
PPLICATIONS
I
NFORMATION
F
IGURE
2A. F
REEZE
D
ATA
I
NPUT
P
ROTOCOL
U
SING
T
HE
O
UTPUT
F
REEZE
C
IRCUITRY
O
VERVIEW
To enable low power states within a system, each output of
ICS87972I (Except QC0 and QFB) can be individually frozen
(stopped in the logic
“
0
”
state) using a simple serial interface
to a 12 bit shift register. A serial interface was chosen to elimi-
nate the need for each output to have its own Output Enable
pin, which would dramatically increase pin count and package
cost. Common sources in a system that can be used to drive
the ICS87972I serial interface are FPGA
’
s and ASICs.
P
ROTOCOL
The Serial interface consists of two pins, FRZ_Data (Freeze
Data) and FRZ_CLK (Freeze Clock). Each of the outputs which
can be frozen has its own freeze enable bit in the 12 bit shift
register. The sequence is started by supplying a logic
“
0
”
start
bit followed by 12NRZ freeze enable bits. The period of each
FRZ_DATA bit equals the period of the FRZ_CLK signal. The
FRZ_DATA serial transmission should be timed so the ICS87972I
can sample each FRZ_DATA bit with the rising edge of the
FRZ_CLK signal. To place an output in the freeze state, a logic
“
0
”
must be written to the respective freeze enable bit in the shift
register. To unfreeze an output, a logic
“
1
”
must be written to the
respective freeze enable bit. Outputs will not become enabled/
disabled until all 12 data bits are shifted into the shift register.
When all 12 data bits are shifted in the register, the next rising
edge of FRZ_CLK will enable or disable the outputs. If the bit
that is following the 12th bit in the register is a logic
“
0
”
, it is used
for the start bit of the next cycle; otherwise, the device will wait
and won
’
t start the next cycle until it sees a logic
“
0
”
bit. Freez-
ing and unfreezing of the output clock is synchronous (see the
timing diagram below). When going into a frozen state, the out-
put clock will go LOW at the time it would normally go LOW, and
the freeze logic will keep the output low until unfrozen. Likewise,
when coming out of the frozen state, the output will go HIGH
only when it would normally go HIGH. This logic, therefore, pre-
vents runt pulses when going into and out of the frozen state.
F
IGURE
2B. O
UTPUT
D
ISABLE
T
IMING
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS87972DYI-147LF | 功能描述:IC CLK MULT/ZD BUFFER 52-LQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:HiPerClockS™ 标准包装:1,000 系列:- 类型:时钟/频率合成器，扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP（8x8） 包装:带卷 (TR) 其它名称:844S012AKI-01LFT |
| ICS87972DYI-147LFT | 功能描述:IC CLK MULT/ZD BUFFER 52-LQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:HiPerClockS™ 标准包装:1,000 系列:- 类型:时钟/频率合成器，扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP（8x8） 包装:带卷 (TR) 其它名称:844S012AKI-01LFT |
| ICS87972DYILF | 功能描述:IC CLK MULT/ZD BUFFER 52-LQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:HiPerClockS™ 标准包装:1,000 系列:- 类型:时钟/频率合成器，扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP（8x8） 包装:带卷 (TR) 其它名称:844S012AKI-01LFT |
| ICS87972DYILFT | 功能描述:IC CLK MULT/ZD BUFFER 52-LQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:HiPerClockS™ 标准包装:1,000 系列:- 类型:时钟/频率合成器，扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP（8x8） 包装:带卷 (TR) 其它名称:844S012AKI-01LFT |
| ICS87973DYI-147LF | 功能描述:IC CLK MULT/ZD BUFFER 52TQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:HiPerClockS™ 标准包装:1,000 系列:- 类型:时钟/频率合成器，扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP（8x8） 包装:带卷 (TR) 其它名称:844S012AKI-01LFT |
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