参数资料
型号: ICS879893AYILF
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟及定时
英文描述: 879893 SERIES, PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48
封装: 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-48
文件页数: 4/16页
文件大小: 187K
代理商: ICS879893AYILF
Integrated
Circuit
Systems, Inc.
879893AYI
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 10, 2005
12
ICS879893I
LOW SKEW, 1-TO-12 (IDCS)
LVCMOS/LVTTL CLOCK GENERATOR
SCHEMATIC EXAMPLE
Figure 1 shows a schematic example of the ICS879893I. In this
example, the CLK1 input is selected as primary. Both CLK0 and
CLK1 inputs are driven by LVCMOS drivers. For the LVCMOS
outputs, series termination is shown in this example. Additional
LVCMOS termination approached are shown in the LVCMOS
Termination Application Note. In this example, feedback trace
is assumed to be a long trace. The series termination near the
QFB pin is required. If the feedback trace is short, series termi-
nation is not required. If this device is also used as a zero delay
buffer, the application note ZDB Delay Affected by Feedback
Trace provides additional information. For the power pins, it is
recommended to have at least one decoupling capacitor per
power pin. The decoupling capacitors should be physically lo-
cated near the power pins
FIGURE 1. ICS879893I SCHEMATIC EXAMPLE
C7
0.1u
Ro=14 Ohm
3.3V LVCMOS/LVTTL
Driv er_LVCMOS
LVCMOS
VDD
VDDO
RD1
Not Install
CLK0
VDD=3.3V
VDD
C6
0.1u
LVCMOS
Zo = 50 Ohm
F_SEL3
F_SEL2
3.3V LVCMOS/LVTTL
LVCMOS/LVTTL
VDDO
VDD
R8
10
F_SEL1
nMAN/A
VDDO
nA
LA
R
M
1
LVCMOS/LVTTL
(U1,48)
To Logic
Input
pins
R2
1K
VDD
C31
0.1u
VDD
C40
10u
(U1,5)
C3
0.1u
(U1,13)
R25
36
VDD
F_SEL0
Status indicator
(U1,44)
(U1,21)
R15
36
R1
1K
Set Logic
Input to
'0'
VDDA
R5
36
R4
36
(U1,17)
CL
K
_
IND
nA
LA
R
M
0
QB5
QA5
Zo = 50 Ohm
U1
ICS879893i
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
36
35
34
33
32
31
30
29
28
27
26
25
48
47
46
45
44
43
42
41
40
39
38
37
GND
QFB
FB
nMAN/A
VDD
CLK0
CLK1
VDD_PLL
nALARM0
nALARM1
CLK_IND
GND
VD
D
QB
5
QB
4
GN
D
VD
D
QB
3
QB
2
GN
D
VD
D
QB
1
QB
0
GN
D
VDD
nALARM_RST
REF_SEL
nPLL_EN
GND
F_SEL0
F_SEL1
GND
F_SEL2
F_SEL3
nOE/MR
VDD
VD
D
QA
5
QA
4
GN
D
VD
D
QA
3
QA
2
GN
D
VD
D
QA
1
QA
0
GN
D
VDD
Ro=14 Ohm
CLK1
LVCMOS/LVTTL
Hardwire Logic Input Pin Examples
VDDO=3.3V
C5
0.1u
C2
0.1u
LVCMOS
RU1
1K
(U1,25)
VDDO
Zo = 50 Ohm
C9
0.1u
Zo = 50 Ohm
C4
0.1u
Driv er_LVCMOS
(U1,40)
RU2
Not Install
Set Logic
Input to
'1'
VDDO
C8
0.1u
C1
0.1u
To Logic
Input
pins
(U1,36)
RD2
1K
R16
36
相关PDF资料
PDF描述
ICS879893AYILF 879893 SERIES, PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48
ICS879893BYI 879893 SERIES, PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48
ICS879893BYIT 879893 SERIES, PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48
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ICS87993AYIT 87993 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
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参数描述
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ICS87993AYILFT 功能描述:IC PLL CLK DRIVER 1-5 32-LQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器,PLL,频率合成器 系列:HiPerClockS™ 标准包装:1,000 系列:- 类型:时钟/频率合成器,扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP(8x8) 包装:带卷 (TR) 其它名称:844S012AKI-01LFT
ICS889474AKLF 功能描述:IC CLK BUFFER MUX 2:2 24-VFQFPN RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟缓冲器,驱动器 系列:HiPerClockS™ 标准包装:74 系列:- 类型:扇出缓冲器(分配) 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 输入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 输出:HCSL,LVDS 频率 - 最大:400MHz 电源电压:3 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN(5x5) 包装:管件
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