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参数资料
| 型号： | ICS87993AYILF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 87993 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封装： | 7 X 7 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, LQFP-32 |
| 文件页数： | 1/16页 |
| 文件大小： | 199K |
| 代理商： | ICS87993AYILF |
87993AYI
www.icst.com/products/hiperclocks.html
REV. B OCTOBER 21, 2004
1
Integrated
Circuit
Systems, Inc.
ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH
GENERAL DESCRIPTION
The ICS87993I is a PLL clock driver designed
specifically for redundant clock tree designs. The
device receives two differential LVPECL clock
signals from which it generates 5 new differen-
tial LVPECL clock outputs. Two of the output pairs
regenerate the input signal frequency and phase while the
other three pairs generate 2x, phase aligned clock outputs.
External PLL feedback is used to also provide zero delay
buffer performance.
The ICS87993I Dynamic Clock Switch (DCS) circuit continu-
ously monitors both input CLK signals. Upon detection of a
failure (CLK stuck HIGH or LOW for at least 1 period), the
INP_BAD for that CLK will be latched (H). If that CLK is the
primary clock, the DCS will switch to the good secondary
clock and phase/frequency alignment will occur with minimal
output phase disturbance. The typical phase bump caused
by a failed clock is eliminated.
HiPerClockS
ICS
FEATURES
5 differential 3.3V LVPECL outputs
Selectable differential clock inputs
CLKx, nCLKx pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
Output frequency range: 50MHz to 250MHz
VCO range: 200MHz to 500MHz
External feedback for “zero delay” clock regeneration
with configurable frequencies
Cycle-to-cycle jitter (RMS): 20ps (maximum)
Output skew: 70ps (maximum), within one bank
3.3V supply voltage
-40°C to 85°C ambient operating temperature
Lead-Free package available
Pin compatible with MPC993
32-Lead QFP (LQFP)
7mm x 7mm x 1.4mm
package body
Y Package
Top View
24 23 22 21 20 19 18 17
1
2
3
4
5
6
7
8
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
VCC
INP0BAD
INP1BAD
CLK_SELECTED
VEE
nEXT_FB
EXT_FB
VEE
nQA1
QA1
nQA0
QA0
VCC
VCCA
MAN_OVERRIDE
PLL_SEL
V
EE
nCLK1
CLK1
CLK_SEL
nCLK0
CLK0
nALARM_RESET
nMR
V
CC
nQB2
QB2
nQB1
QB1
nQB0
QB0
V
CC
ICS87993I
PIN ASSIGNMENT
BLOCK DIAGRAM
PLL
÷2
÷4
Dynamic Switch
Logic
nQB0
QB0
nQB1
QB1
nQB2
QB2
nQA0
QA0
nQA1
QA1
PLL_SEL
CLK_SELECTED
INP1BAD
INP0BAD
MAN_OVERRIDE
ALARM_RESET
SEL_CLK
nCLK0
CLK0
nCLK1
CLK1
nEXT_FB
EXT_FB
nMR
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相关代理商/技术参数 |
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| ICS87993AYILFT | 功能描述:IC PLL CLK DRIVER 1-5 32-LQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:HiPerClockS™ 标准包装:1,000 系列:- 类型:时钟/频率合成器，扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP（8x8） 包装:带卷 (TR) 其它名称:844S012AKI-01LFT |
| ICS889474AKLF | 功能描述:IC CLK BUFFER MUX 2:2 24-VFQFPN RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟缓冲器，驱动器 系列:HiPerClockS™ 标准包装:74 系列:- 类型:扇出缓冲器（分配） 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 输入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 输出:HCSL，LVDS 频率 - 最大:400MHz 电源电压:3 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:管件 |
| ICS889474AKLFT | 功能描述:IC CLK BUFFER MUX 2:2 24-VFQFPN RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟缓冲器，驱动器 系列:HiPerClockS™ 标准包装:74 系列:- 类型:扇出缓冲器（分配） 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 输入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 输出:HCSL，LVDS 频率 - 最大:400MHz 电源电压:3 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:管件 |
| ICS889831AKLF | 功能描述:IC CLK BUFF 1:4 2.1GHZ 16-VFQFPN RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟缓冲器，驱动器 系列:HiPerClockS™ 标准包装:1 系列:HiPerClockS™ 类型:扇出缓冲器（分配），多路复用器 电路数:1 比率 - 输入:输出:2:18 差分 - 输入:输出:是/无 输入:CML，LVCMOS，LVPECL，LVTTL，SSTL 输出:LVCMOS，LVTTL 频率 - 最大:250MHz 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:- 其它名称:800-1923-6 |
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