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| 型号： | ICS889872AKLFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION |
| 中文描述： | 889872 SERIES, LOW SKEW CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC16 |
| 封装： | 3 X 3 MM, 0.95 MM HEIGHT, ROHS COMPLIANT, MO-220VEED-2/-4, VFQFN-16 |
| 文件页数： | 11/14页 |
| 文件大小： | 649K |
| 代理商： | ICS889872AKLFT |
ICS889872
DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
PRELIMINARY
IDT / ICS
LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
11
ICS889872AK REV. A AUGUST 22, 2007
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS889872.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS889872 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
DD
= 2.5V + 5% = 2.625V, which gives worst case results.
Power_
MAX
= V
DD_MAX
* I
DD_MAX
= 2.625V * 80mA =
210mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj =
θ
JA
* Pd_total + T
A
Tj = Junction Temperature
θ
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
θ
JA
must be used. Assuming no air flow
and a multi-layer board, the appropriate value is 51.5°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.210W * 51.5°C/W = 95.8°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (single layer or multi-layer).
Table 6. Thermal Resistance
θ
JA
for 16 Lead VFQFN, Forced Convection
θ
JA
by Velocity
0
Linear Feet per Minute
Multi-Layer PCB, JEDEC Standard Test Boards
51.5°C/W
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