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参数资料
| 型号： | ICS894D115BGI-01T |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 1/16页 |
| 文件大小： | 0K |
| 描述： | IC CLK/DATA RECOVERY 20-TSSOP |
| 标准包装： | 2,500 |
| 系列： | HiPerClockS™ |
| 类型： | 时钟和数据恢复（CDR），多路复用器 |
| PLL： | 是 |
| 主要目的： | STM-1，STM-4 |
| 输入： | LVPECL |
| 输出： | LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 622.08MHz |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 20-TSSOP |
| 包装： | 带卷 (TR) |
| 其它名称： | 894D115BGI-01T |
OC-12/STM-4 AND OC-3/STM-1
CLOCK/DATA RECOVERY DEVICE
ICS894D115I-01
IDT / ICS CLOCK/DATA RECOVERY DEVICE
1
ICS894D115BGI-01 REV. C OCTOBER 15, 2008
General Description
The ICS894D115I-01 is a clock and data recovery
circuit. The device is designed to extract the clock
signal from a NRZ-coded STM-4 (OC-12/STS-12) or
STM-1 (OC-3/STS-3) input data signal. The output
signals of the device are the recovered clock and
retimed data signals. Input and output are differential signals for
best signal integrity and to support high clock and data rates. All
control inputs and outputs are single-ended signals. An internal
PLL is used for clock generation and recovery. An external clock
input is provided to establish an initial operating frequency of the
clock recovery PLL and to provide a clock reference in the
absence of serial input data. The device supports a signal detect
input and a lock detect output. A bypass circuit is provided to
facilitate factory tests.
Features
Clock recovery for STM-4 (OC-12/STS-12) and
STM-1 (OC-3/STS-3)
Input: NRZ data (622.08 or 155.52 Mbit/s)
Output: clock signal (622.08MHz or 155.52MHz) and retimed
data signal at 622.08 or 155.52 Mbit/s
Internal PLL for clock generation and clock recovery
Differential inputs can accept LVPECL levels
Differential LVPECL data and clock outputs
Lock reference input and PLL lock output
19.44MHz reference clock input
Full 3.3V supply mode
-40°C to 85°C operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
See ICS894D115I for a clock/data recovery circuit with a
TSSOP EPAD package
See ICS894D115I-04 for a clock/data recovery circuit with
LVDS outputs
HiPerClockS
ICS
Block Diagram
Pin Assignment
ICS894D115I-01
20-Lead TSSOP
6.5mm x 4.4mm x 0.925mm
package body
G Package
Top View
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VEE
LOCK_REFN
REF_CLK
STS12
LOCK_DET
VEE_PLL
nDATA_IN
DATA_IN
VCCA
VCC
VCCA
VEE_PLL
CAP
nCAP
BYPASS
SD
DATA_OUT
nDATA_OUT
CLK_OUT
nCLK_OUT
LOCK_DET
DATA_OUT
nDATA_OUT
CLK_OUT
nCLK_OUT
STS12
nCAP
CAP
BYPASS
DATA_IN
nDATA_IN
SD
LOCK_REFN
REF_CLK
PLL
0
1
Pullup/Pulldown
Pulldown
Pullup
相关PDF资料 |
PDF描述 |
|---|---|
| VE-B4F-IU | CONVERTER MOD DC/DC 72V 200W |
| ICS894D115BGI-01LFT | IC CLK/DATA RECOVERY 20-TSSOP |
| VE-B41-IU | CONVERTER MOD DC/DC 12V 200W |
| ICS894D115AGI-04LFT | IC CLK/DATA RECOVERY 20-TSSOP |
| VI-B4H-IU | CONVERTER MOD DC/DC 52V 200W |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS8S58035AKILF | 功能描述:IC CLOCK BUFFER MUX 2:6 32-VFQFN RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟缓冲器，驱动器 系列:HiPerClockS™ 标准包装:74 系列:- 类型:扇出缓冲器（分配） 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 输入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 输出:HCSL，LVDS 频率 - 最大:400MHz 电源电压:3 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:管件 |
| ICS8S58035AKILFT | 功能描述:IC CLOCK BUFFER MUX 2:6 32-VFQFN RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟缓冲器，驱动器 系列:HiPerClockS™ 标准包装:74 系列:- 类型:扇出缓冲器（分配） 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 输入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 输出:HCSL，LVDS 频率 - 最大:400MHz 电源电压:3 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:管件 |
| ICS8S73034AGILF | 制造商:Integrated Device Technology Inc 功能描述:IC DIVIDER LVPECL 16-TSSOP |
| ICS8S73034AGILFT | 制造商:Integrated Device Technology Inc 功能描述:IC DIVIDER LVPECL 16-TSSOP |
| ICS8S73034AMILF | 制造商:Integrated Device Technology Inc 功能描述:IC DIVIDER LVPECL 16-SOIC |
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