- 您现在的位置：买卖IC网 > PDF目录65533 > ICS9112CM-18 PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 PDF资料下载
参数资料
| 型号： | ICS9112CM-18 |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封装： | 0.150 INCH, SOIC-16 |
| 文件页数： | 1/5页 |
| 文件大小： | 84K |
| 代理商： | ICS9112CM-18 |
ICS9112CM-18
MDS 9112CM-18 B
1
Revision 021903
In tegr ated C i r cu i t S y st ems q 5 25 Ra ce Str eet, San Jose, C A 95 126 q tel ( 408) 2 95-9 800 q
w w w.ic s t .c o m
ZERO DELAY, LOW SKEW BUFFER
Description
The ICS9112CM-18 is a low jitter, low skew, high
performance Phase Lock Loop (PLL) based zero delay
buffer for high speed applications. Based on ICS’
proprietary low jitter PLL techniques, the device
provides eight low skew outputs at speeds up to 160
MHz at 3.3V. The ICS9112-18 includes a bank of four
outputs running at 1/2X. In the zero delay mode, the
rising edge of the input clock is aligned with the rising
edges of all eight outputs. Compared to competitive
CMOS devices, the ICS9112CM-18 has the lowest
jitter.
ICS manufactures the largest variety of clock
generators and buffers and is the largest clock supplier
in the world.
The older ICS9112BM-18 is not recommended for
new designs.
Features
Packaged in 16 pin SOIC
Zero input-output delay
Four 1X outputs plus four 1/2X outputs
Output to output skew is less than 250 ps
Output clocks up to 160 MHz at 3.3V
Ability to generate 2X the input
Full CMOS outputs with 18 mA output drive
capability at TTL levels at 3.3V
Spread SmartTM technology works with spread
spectrum clock generators
Advanced, low power, sub micron CMOS process
Operating voltage of 3.3V or 5V
Block Diagram
CLKA4
CLKB1
CLKA3
CLKB2
CLKB3
CLKA2
CLKA1
CLKB4
Control
Logic
S1, S0
2
PLL
FBIN
CLKIN
/2
VDD
2
GND
2
BANK
A
BANK
B
相关PDF资料 |
PDF描述 |
|---|---|
| ICS9112M-16LF | 91 SERIES, LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| ICS9112M-16 | 91 SERIES, LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| ICS9112M-16-T | LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| ICS9112M-16LF | 91 SERIES, LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| ICS9112M-18T | 91 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS9112M-06 | 制造商:Integrated Device Technology Inc 功能描述: |
| ICS9112M-07 | 制造商:ICS 制造商全称:ICS 功能描述:Low Skew Output Buffer |
| ICS9112M-22 | 功能描述:IC CLK BUFFER DVR 133MHZ 8-SOIC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟缓冲器，驱动器 系列:- 标准包装:74 系列:- 类型:扇出缓冲器（分配） 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 输入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 输出:HCSL，LVDS 频率 - 最大:400MHz 电源电压:3 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:管件 |
| ICS9112M-31 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator for Fibre Channel Systems |
| ICS9112M-32 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator for Fibre Channel Systems |
发布紧急采购，3分钟左右您将得到回复。