参数资料
型号: ICS9120M-45LF
元件分类: 时钟产生/分配
英文描述: 50 MHz, OTHER CLOCK GENERATOR, PDSO8
封装: 0.150 INCH, SOIC-8
文件页数: 3/5页
文件大小: 76K
代理商: ICS9120M-45LF
3
ICS9120-45
Absolute Maximum Ratings
Electrical Characteristics at 5 V
* Parameter is guaranteed by design and characterization. Not 100% tested in production.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect product reliability.
AVDD,VDD referenced to GND . . . . . . . . . . . . . . . . 7V
Operating temperature under bias. . . . . . . . . . . . . . . . 0°C to +70°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Voltage on I/O pins referenced to GND. . . . . . . . . . . GND -0.5V to VDD +0.5V
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 Watts
VDD = +4.5 to +5.5 V, TA = 0-70
oC unless otherwise stated
DC Characteristics
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Input Low Voltage
V
IL
--
0.8
V
Input High Voltage
V
IH
2.0
-
V
Input Low Current
I
IL
VIN=0V (For -09 only)
-
-8.3
-18.0
A
Input High Current
I
IH
VIN=VDD (For -09 only)
-
5.0
A
Output Low Voltage
V
OL*
IOL=+10mA
-
0.15
0.4
V
Output High Voltage
V
OH
*
IOH=-30mA
2.4
3.7
-
V
Output Low Current
I
OL
*
VOL=0.8V
25.0
45.0
-
mA
Output High Current
I
OH
*
VOH=2.4V
-
-53.0
-35.0
mA
Supply Current
I
CC
Unloaded
-
22.0
50.0
mA
Supply Current
I
CC
Unloaded (For -09 only)
-
180.0
500.0
A
Pull-up Resistor Value
R
pu
*
(For -09 only)
-
400.0
800.0
k ohm
AC Characteristics
Rise Time 0.8 to 2.0V
T
r
*
15pF load
-
0.9
2.0
ns
Fall Time 2.0 to 0.8V
T
f*
15pF load
-
0.7
1.5
ns
Rise Time 20% to 80%
T
r*
15pF load
-
1.8
3.25
ns
Fall Time 80% to 20%
T
f*
15pF load
-
1.4
2.5
ns
Duty Cycle
D
t*
15pF load @ 50% of VDD;
Except REFCLK
45.0
50.0
55.0
%
Duty Cycle
D
t*
15pf load @ 50% of VDD;
REFCLK only
40.0
50.0
60.0
%
Jitter, One Sigma
T
jis
*
For all frequencies except
REFCLK
-
85.0
-
ps
Jitter, Absolute
T
jab
For all frequencies except
REFCLK
-700.0
380.0
700.0
ps
Jitter, One Sigma
T
jis*
REFCLK only
-
266.0
600.0
ps
Jitter, Absolute
T
jab
REFCLK only
-1.5
380.0
1.5
ns
Input Frequency
F
i
*
11.0
14.0
17.0
MHz
Output Frequency
F
o
*
11.0
-
42.0
MHz
Power-up Time
T
pu
*
0 to 33.8 MHz
-
5.5
12.0
ms
Crystal Input Capacitance
C
inx
*
X1 (Pin 1)# X2 (Pin 8; -08 only)
-
5
-
pF
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