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参数资料
| 型号： | ICS9147F-08LF |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | SSOP-48 |
| 文件页数： | 2/7页 |
| 文件大小： | 272K |
| 代理商： | ICS9147F-08LF |
2
ICS9147-08
Pin Descriptions
Functionality with (14.31818 MHz input)
Output Enable
(pin 13) Function
* Bidirectional input/output pins, input logic level determined at internal power-on-reset are latched. Use 10Kohm resistor to
program logic Hi toVDD or GND for logic low. Internal input has No pullup or pulldown.
**Test: is the frequency applied to the X1 input. Can be crystal or
tester generated clock overriding crystal at X1 pin.
Address Select
CPUL
(1:2)
CPUH
SDRAM
(1:12)
BUS (1:6)
(MHz)
20M
(MHz)
48M
(MHz)
SLOW#
FS1
FS0
(MHz)
BSEL=1
BSEL=0
(MHz)
0
30.0
15.0
34.3
20
48
0
1
33.3
16.7
34.3
20
48
0
1
0
83.3
41.65
34.3
20
48
0
1
TEST/2
TEST/4
TEST/7
TEST/12 TEST/5
1
0
60.0
30.0
34.3
20
48
1
0
1
66.6
33.3
34.3
20
48
1
0
75.0
37.5
34.3
20
48
1
100.0
50.0
34.3
20
48
OE
CPUL, CPUH, SDRAM,
BUS, 20, 48, REF
0Tristate
1
Running
PIN N U M BE R
PIN N A M E
TY P E
DE S C R IP TI O N
2
R EF
OU T
Reference clock output*
F S 1
IN
Logic input frequency select Bit1*. Input latched at Poweron.
3, 9, 16, 22,
27, 33, 39, 45
GND
P WR
Ground.
4
X1
IN
Crystal input. Nominally 14.318 MHz. (External crystal load caps required)
5
X2
OU T
Crystal output. (External crystal load caps required)
41
VDDL
P WR
2.5 or 3.3V buffer power for CPUL and IOAPIC output buffers.
8, 10, 11, 12, 14,
BUS (1:5)
OU T
BUS clock outputs. see select table for frequency
15
BUS6
OUT
BUS clock output. See select table for frequency.*
FS0
IN
Logic input frequency select Bit0.*. Input latched at Poweron.
23
OE
IN
Logic input for output enable, tristates all outputs when low. Has a 40Kohm
pullup to VDD.
24
SLOW#
IN
Logic input to frequency select table, has 40k ohm pullup to VDD, will smoothly
transition 60 or 66.6 MHz to half speed when input goes to low
47
20M
OU T
20 MHz fixed clock* (Freq is < 1PPM accurate with exact 14.318 MHz input)
BSEL
IN
Logic input* for selecting synchronous or asynchronous BUS frequency- see table
above. Input latched at Poweron.*
1, 6, 13, 19,
30, 36, 48
VDD
P WR
3.3 volt core logic and buffer power
17, 18, 20, 21, 28,
29, 31, 32, 34,
35, 37, 38
SDRAM (1:12)
OU T
SDRAM clocks at CPU speed. See select table for frequency.
40
CPUH
OU T
CPU clock operates at SDRAM VDD level (3.3V nom).
42, 43
CPUL (1:2)
OU T
CPU clock output clocks .See select table for frequency. Operates at down to
2.5V controlled by VDDL pin.
7, 25, 26
N/C
—
Pins not internally connected.
46
48M
OU T
48 MHz fixed clock output.
44
IOA PIC
OU T
Reference clock (14.318MHz) powered by VDDL,
operating 2.5 to 3.3V.
相关PDF资料 |
PDF描述 |
|---|---|
| ICS9147F-PPP-LF | 83.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS9147F-22 | 83.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS9148M-60LF | 133.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
| ICS9148F-60LF | 133.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
| ICS9158-05M | 66.7 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO24 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS9147F-08T | 制造商:ICS 功能描述: |
| ICS9147F-09 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator & Integrated Buffers for 686 Series CPUs |
| ICS9147F-12 | 制造商:ICS 制造商全称:ICS 功能描述:Pentium/ProTM System and Cyrix⑩ Clock Chip |
| ICS9147F-14 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator & Integrated Buffers for PENTIUM/ProTM |
| ICS9147F-16 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator & Integrated Buffers for PENTIUMTM |
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