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参数资料
| 型号： | ICS9148YF-17-T |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 100.2 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | 0.300 INCH, SSOP-48 |
| 文件页数： | 14/15页 |
| 文件大小： | 466K |
| 代理商： | ICS9148YF-17-T |
8
ICS9148-17
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9148-17. It is used to turn off the PCICLK (0:5) clocks for low power operation.
PCI_STOP# is synchronized by the ICS9148-17 internally.The minimum that the PCICLK (0:5) clocks are enabled (PCI_STOP#
high pulse) is at least 10 PCICLK (0:5) clocks. PCICLK (0:5) clocks are stopped in a low state and started with a full high pulse
width guaranteed. PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK
(Free-running)
CPU_STOP#
(High)
PCICLK
(External)
PCI_STOP#
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9148.
3. All other clocks continue to run undisturbed.
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相关代理商/技术参数 |
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|---|---|
| ICS9148YF-36 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator & Integrated Buffers for PENTIUM/ProTM |
| ICS9148YF-46 | 制造商:ICS 制造商全称:ICS 功能描述:Pentium/ProTM System Clock Chip |
| ICS9148YF-60 | 制造商:ICS 制造商全称:ICS 功能描述:Pentium/ProTM System Clock Chip |
| ICS9148YF-82 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator & Integrated Buffers for PENTIUM/ProTM |
| ICS9150-01 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:Pentium Pro? and SDRAM Frequency Generator |
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