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参数资料
| 型号： | ICS9148YF-82LF |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | 0.300 INCH, SSOP-48 |
| 文件页数： | 14/16页 |
| 文件大小： | 829K |
| 代理商： | ICS9148YF-82LF |
7
ICS9148-82
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CPU_STOP# is synchronized by the ICS9148-82. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100
CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in
a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4
CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS9148-82.
3. All other clocks continue to run undisturbed. (including SDRAM outputs).
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相关代理商/技术参数 |
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|---|---|
| ICS9150-01 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:Pentium Pro? and SDRAM Frequency Generator |
| ICS9150-02 | 制造商:ICS 制造商全称:ICS 功能描述:Pentium Pro™ and SDRAM Frequency Generator |
| ICS9150-04 | 制造商:ICS 制造商全称:ICS 功能描述:Pentium Pro⑩ and SDRAM Frequency Generator |
| ICS9150-08 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator & Integrated Buffers for Pentium/Pro⑩ |
| ICS9150F-01 | 制造商:ICS 功能描述: |
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