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参数资料
| 型号： | ICS9159C-02CW28 |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
| 封装： | 0.300 INCH, SOIC-28 |
| 文件页数： | 6/7页 |
| 文件大小： | 312K |
| 代理商： | ICS9159C-02CW28 |
6
ICS9159C-02
Electrical Characteristics at 5.0 V
VDD = 4.5 - 5.5 V, TA = 0 - 70oC unless otherwise stated
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
AC Characteristics
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Rise Time
1
Tr1
20pF load, 0.8 to 2.0V
PCLK & BCLK
-
0.55
0.95
ns
Fall Time
1
Tf1
20pF load, 2.0 to 0.8V
PCLK & BCLK
-
0.52
0.90
ns
Rise Time
1
Tr2
20pF load, 20% to 80%
PCLK & BCLK
-
1.2
2.1
ns
Fall Time
1
Tf2
20pF load, 80% to 20%
PCLK & BCLK
-
1.1
2.0
ns
Duty Cycle
1
Dt
20pF load @ VOUT=50%
45
50
55
%
Duty Cycle
1
Dt2
20pF load @ VOUT=1.4V
%
Jitter, One Sigma
1
Tj1s1
PCLK & BCLK Clocks;
Load=20pF, RS=33
FOUT>25 MHz
-
50
150
ps
Jitter, Absolute
1
Tjab1
PCLK & BCLK Clocks;
Load=20pF, RS=33
FOUT>25 MHz
-250
-
250
ps
Jitter, One Sigma
1
Tj1s2
Fixed CLK; Load=20pF RS=33
-
1
3
%
Jitter, Absolute
1
Tjab2
Fixed CLK; Load=20pF RS=33
-5
2
5
%
Input Frequency
1
Fi
12.0
14.318
16.0
MHz
Logic Input
Capacitance
1
CIN
Logic input pins
-
5
-
pF
Crystal Oscillator
Capacitance1
CINX
X1, X2 pins
-
18
-
pF
Power-on Time
1
ton
From VDD=1.6V to 1st crossing of
66.5 MHz VDD supply ramp<40ms
-
2.5
4.5
ms
Frequency Settling
Time
1
ts
From 1st crossing of acquisition to
<1% settling
-
2.0
4.0
ms
Clock Skew
Window
1
Tsk1
PCLK to PCLK;
Load=20pF; @1.4V
-
150
250
ps
Clock Skew
Window
1
Tsk2
BCLK to BCLK;
Load=20pF; @1.4V
-
300
500
ps
Clock Skew
Window
1
Tsk3
PCLK to BCLK;
Load=20pF; @1.4V
1
2.6
5
ns
相关PDF资料 |
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