参数资料
型号: ICS9169CM-272
元件分类: 时钟产生/分配
英文描述: 83.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO32
封装: SOIC-32
文件页数: 2/8页
文件大小: 369K
代理商: ICS9169CM-272
2
ICS9169C-272
Pin Descriptions
PIN NUM BER
PIN NAM E
TYPE
DESCRIPTIO N
1
VDD
PW R
Power for device logic and crystal oscillator circuit and
14.318 M H z output.
2X1
IN
XTAL or external reference frequency input. This input
includes XTA L load capacitance and feedback bias for a
12-16M Hz crystal, nom inally 14.31818M H z external crystal
load of 30pF to GND recom m ended for VDD pow er on faster
than 2.0m s.
3
X 2
OUT
XTAL output w hich includes XTAL load capacitance.
External crystal load of 10pF to GND recom m ended for VDD
power on faster than 2.0m s.
4,11,20,26
G N D
PW R
Ground for device logic.
5
CPU(1)
OUT
Processor clock output which is a m ultiple of the input
reference frequency.
FS0
IN
Frequency m ultiplier select pins. 350K internal pull up.
6,7,9,10,15,16,17,18,19
CPU
(2:5) (8:12)
OUT
Processor clock outputs w hich are a m ultiple of the input
reference frequency.
8
VDDC1
PW R
Pow er for CPU (1:6) output buffers only. Can be reduced V DD
for 2.5V (2.375-2.62V ) next generation processor clocks.
12
CPU(6)
OUT
Processor clock output which is a m ultiple of the input
reference frequency internal pull up devices.
FS1
IN
Frequency m ultiplier select pin. See shared pin description.
350K internal pull up.
13
CPU(7)
OUT
Processor clock output which is a m ultiple of the input
reference frequency internal pull up devices.
FS2
IN
Frequency m ultiplier select pin. See shared pin description.
350K internal pull up.
14
VDDC2
PW R
Power for CPU PLL, logic and CPU(7:12)output buffers. M ust
be nom inal 3.3V (3.0 to 3.7V).
21,22,24,25,27,28
BUS (1:6)
OU T
BU S clock outputs w hich are a m ultiple of the input reference
clock.
23
VDDB
PW R
Power for BUS clock buffers BU S(1:6).
29
VDDF
PW R
Power for fixed clock buffer (48 M H z, 24 M hz).
30
24M H z
OUT
Fixed 24M Hz clock (assum ing a 14.31818M H z REF
frequency).
31
48M H z
OUT
Fixed 48M Hz clock (assum ing a 14.31818M H z REF
frequency).
32
REF
OUT
Fixed 14.31818M H z clock (assum ing a 14.31818M Hz REF
frequency).
BSEL
IN
Selection for synchronous or asynchronous bus clock
operation. See shared pin program m ing description late in this
data sheet for further explanation. 350K internal pull up.
* The internal pull up will vary from 350K
to 500K based on temperature
相关PDF资料
PDF描述
ICS9175-05CS16 60 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO16
ICS9175-06CN16 52 MHz, PROC SPECIFIC CLOCK GENERATOR, PDIP16
ICS9175-06CS16W 52 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO16
ICS9175-04CS16W 66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO16
ICS9175-05CN16LF 60 MHz, PROC SPECIFIC CLOCK GENERATOR, PDIP16
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