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参数资料
| 型号： | ICS91719YG-T |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封装： | 4.40 MM, 0.65 MM PITCH, MO-153, TSSOP-16 |
| 文件页数： | 9/10页 |
| 文件大小： | 69K |
| 代理商： | ICS91719YG-T |
8
ICS91719
0506C—07/28/03
Absolute Maximum Ratings
Stresses above those listed under
Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 V
Voltage on any pin with respect to GND . . . -0.5 to +7.0 V
Storage Temperature . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Operating Temperature . . . . . . . . . . . . . . . . . . 0°C to +85°C
Ambient Operating Temperature under Bias . -55 to +125 °C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . 0.5 W
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 85°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Voltage
VIH
2VDD + 0.3
V
Input Low Voltage
VIL
VSS - 0.3
0.8
V
Input High Current
IIH
VIN = VDD
-5
5
mA
Input Low Current
IIL1
VIN = 0 V; Inputs with no pull-up resistors
-5
mA
Powerdown Current
IDD3.3PD
35
mA
Input Frequency
Fi
VDD = 3.3 V
14.318
MHz
Input Crystal Frequency
FCYI
14.318
Typ + 10%
MHz
Input Clock Frequency
FCLKI
80
MHz
Pin Inductance
Lpin
7nH
Input Capacitance
1
CIN
Logic Inputs
5
pF
COUT
Output pin capacitance
6
pF
CINX
X1 & X2 pins
27
36
45
pF
Transition time
1
Ttrans
To 1st crossing of target frequency
3
ms
Settling time
1
Ts
From 1st crossing to 1% target frequency
3
ms
Clk Stabilization
1
TSTAB
From VDD = 3.3 V to 1% target frequency
1
3
ms
Delay
1
tPZH,tPZL
Output enable delay (all outputs)
1
10
ns
1Guaranteed by design, not 100% tested in production.
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