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参数资料
| 型号： | ICS91720YG-T |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 91720 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 封装： | 4.40 MM, 0.65 MM PITCH, MO-153, TSSOP-8 |
| 文件页数： | 5/11页 |
| 文件大小： | 91K |
| 代理商： | ICS91720YG-T |
3
ICS91720
0698D—10/05/04
Table 1: Frequency Configuration Table
(See I2C Byte 0)
Above is the hard coded 5 bit (32 entry) ROM table.
FS2:0 are ONLY accessible through I2C software programming bits (byte0 bits5:7). FS3 and FS4 can also be
decoded from FS_IN0:1 latched input hardware pins.
FS_IN0
→ FS3 and FS_IN1 → FS4. Upon power-up the default is to use hardware selections of FS_IN0:1 latched
values.
FS2
= 0, FS1 = 0, FS0 = 1 upon power-up (refer to the functionality table on page 1).
To access non-default spread entries in the ROM, byte0 programming should be used. In order to change the power
up default of FS_IN1:0 = 10 (-1.25% down spread) to any other spread % entry, first change byte0bit 0 to software
selection by switching this bit to a ‘1’ and then program the desired percentage by changing byte0 bits 7:3.
FS4
FS3
FS2
FS1
FS0
Sprd Type Sprd %
00
0
0.60
00
0
1
0.80
00
0
1
0
1.00
00
0
1
1.25
00
1
0
1.50
00
1
0
1
2.00
00
1
0
0.50
00
1
1.00
01
0
0.60
01
0
1
1.00
0
1
0
1
0
-0.80
0
1
0
1
1 CNTR SPD
+/-0.3
01
1
0
1.50
01
1
0
1
1.75
01
1
0
2.00
01
1
2.50
10
0
3.00
10
0
1
-1.25
10
0
1
0
0.40
10
0
1
0.50
10
1
0
0.70
10
1
0
1
1.00
10
1
0
1.20
10
1
1.50
11
0
0.60
11
0
1
0.80
11
0
1
0
1.00
11
0
1
1.25
11
1
0
1.50
11
1
0
1
2.00
11
1
0
0.50
11
1
1.00
48in/48out
66in/66out
DOWN
SPREAD
(-)
CENTER SPD
(+/-)
14in/27out
DOWN
SPREAD
(-)
CENTER SPD
(+/-)
14in/14out
27in/27out
DOWN
SPREAD
(-)
DOWN
SPREAD
(-)
CENTER
SPREAD
(+/-)
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