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参数资料
| 型号： | ICS9179F-06 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 16 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封装： | SSOP-48 |
| 文件页数： | 2/8页 |
| 文件大小： | 496K |
| 代理商： | ICS9179F-06 |
2
ICS9179-06
Pin Descriptions
Power Groups
VDD = Power supply for OUTPUT buffers
VDDS = Power supply for I2C circuitry
VDDA= Power supply forAnalog PLL circuitry
Notes:
1.
At power up all sixteen outputs are enabled and active.
2.
OE has a 100K Ohm internal pull-up resistor to keep all outputs active.
3.
The SDATA and SCLK inputs both also have internal pull-up resistors with values above 100K Ohms as well for
complete platform flexibility.
4.
I2C Byte0, bits 0 & 1 used to select delay. Default* values at power up is 0
5.
Subject to design engineering verification of target value.
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Ground Groups
GND = Ground supply for OUTPUT buffer
GNDS = Ground supply for I2C circuitry
GNDA= Ground supply forAnalog PLL circuitry
Delay Selection Table
4
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