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参数资料
| 型号： | ICS9248YF-101 |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 137 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | SSOP-48 |
| 文件页数： | 14/16页 |
| 文件大小： | 344K |
| 代理商： | ICS9248YF-101 |
7
ICS9248-101
CLK_STOP# Timing Diagram
CLK_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CLK_STOP# is synchronized by the ICS9248-101. The minimum that the CPU clock is enabled (CLK_STOP# high pulse) is 100
CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in
a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4
CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CLK_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS9248-101.
3. SDRAM-F output is controlled by Buffer in signal, not affected by the ICS9248-101
CLK_STOP# signal. SDRAM [7:0] are controlled as shown.
4. All other clocks continue to run undisturbed.
PCICLK [6:0]
SDRAM [7:0]
CPUCLK [2:0]
CPUCLK _F
SDRAM_F
PCI_STOP# (High)
CLK_STOP#
INTERNAL
CPUCLK
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| ICS9248YF-126-T | 150 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS9248YF-126LF | 150 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS9248YF-141LF-T | 166.66 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS9248YF-103 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator & Integrated Buffers for PENTIUM/ProTM |
| ICS9248YF-107 | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Timing Generator for PENTIUM II Systems |
| ICS9248YF-110 | 制造商:ICS 制造商全称:ICS 功能描述:AMD-K7TM System Clock Chip |
| ICS9248YF-112-T | 制造商:ICS 制造商全称:ICS 功能描述:Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ |
| ICS9248YF-114-T | 制造商:ICS 制造商全称:ICS 功能描述:AMD - K7⑩ System Clock Chip |
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